Datasheet AD8324 (Analog Devices) - 9
| 制造商 | Analog Devices |
| 描述 | 3.3 V DOCSIS 2.0 Upstream Cable Line Driver |
| 页数 / 页 | 16 / 9 — Data Sheet. AD8324. –10. CH PWR. 12dBm. OUT = 57dBmV/TONE. WORST ACP … |
| 修订版 | C |
| 文件格式/大小 | PDF / 427 Kb |
| 文件语言 | 英语 |
Data Sheet. AD8324. –10. CH PWR. 12dBm. OUT = 57dBmV/TONE. WORST ACP –61dBc. @ MAX GAIN. –20. –30. –40. m B. –50. (dBmV. –60. OUTV. –70. –80. CU1. –90. CL1. –100
该数据表的模型线
文件文字版本
Data Sheet AD8324 0 60 V –10 CH PWR 12dBm OUT = 57dBmV/TONE WORST ACP –61dBc 50 @ MAX GAIN –20 40 –30 30 ) –40 ) 20 m B –50 (d 10 T (dBmV OU –60 0 P OUTV –70 –10 –80 –20 CU1 CU1 –90 C0 C0
-013 0
–30
39-
CL1 CL1 –100
043
–40
04339-0-016
CENTER 21 MHz 100 kHz/DIV SPAN 1 MHz 41.6 41.7 41.8 41.9 42.0 42.1 42.2 42.3 42.4 42.5 FREQUENCY (MHz)
Figure 13. Adjacent Channel Power Figure 16. Two-Tone Intermodulation Distortion
40 0 TXEN = 0 –10 V 30 IN = 27.5dBmV DEC60 –20 20 DEC54 –30 DEC48 ) 10 B ) DEC42 d –40 B ( d ( 0 DEC36 ION –50 IN T DEC30 A GA L –60 –10 O DEC24 IS DEC18 –70 –20 DEC12 –80 MAX GAIN –30 DEC 1 TO DEC 6
14 17 0
–90
0 -0- 0-
MIN GAIN
9- 339
–40
433 04
–100
0
0.1 1 10 100 1000 1 10 100 1000 FREQUENCY (MHz) FREQUENCY (MHz)
Figure 14. AC Response Figure 17. Isolation in Transmit Disable Mode vs. Frequency
1.4 2.0 f = 10MHz 1.3 1.5 ) 1.2 1.0 B d 1.1 0.5 f = 5MHz 1.0 ROR (dB) 0 R f = 10MHz STEP SIZE ( T 0.9 –0.5 f = 42MHz TPU GAIN E OU 0.8 –1.0 f = 65MHz 0.7 –1.5 0.6
04339-0-015
–2.0
04339-0-018
0 6 12 18 24 30 36 42 48 54 60 0 6 12 18 24 30 36 42 48 54 60 GAIN CONTROL (Decimal Code) GAIN CONTROL (Decimal Code)
Figure 15. Output Step Size vs. Gain Control Figure 18. Gain Error vs. Gain Control for Various Frequencies Rev. C | Page 9 of 16 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS LOGIC INPUTS (TTL-/CMOS-COMPATIBLE LOGIC) TIMING REQUIREMENTS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TEST CIRCUIT APPLICATIONS INFORMATION GENERAL APPLICATIONS CIRCUIT DESCRIPTION GAIN PROGRAMMING FOR THE AD8324 INPUT BIAS, IMPEDANCE, AND TERMINATION OUTPUT BIAS, IMPEDANCE, AND TERMINATION POWER SUPPLY SIGNAL INTEGRITY LAYOUT CONSIDERATIONS INITIAL POWER-UP RAMP PIN AND BYP PIN FEATURES POWER SAVING FEATURES DISTORTION, ADJACENT CHANNEL POWER, AND DOCSIS UTILIZING DIPLEX FILTERS NOISE AND DOCSIS DIFFERENTIAL SIGNAL SOURCE DIFFERENTIAL SIGNAL FROM SINGLE-ENDED SOURCE SINGLE-ENDED SOURCE OUTLINE DIMENSIONS ORDERING GUIDE
-013 0
–30
39-
CL1 CL1 –100
043
–40
04339-0-016
CENTER 21 MHz 100 kHz/DIV SPAN 1 MHz 41.6 41.7 41.8 41.9 42.0 42.1 42.2 42.3 42.4 42.5 FREQUENCY (MHz)
Figure 13. Adjacent Channel Power Figure 16. Two-Tone Intermodulation Distortion
40 0 TXEN = 0 –10 V 30 IN = 27.5dBmV DEC60 –20 20 DEC54 –30 DEC48 ) 10 B ) DEC42 d –40 B ( d ( 0 DEC36 ION –50 IN T DEC30 A GA L –60 –10 O DEC24 IS DEC18 –70 –20 DEC12 –80 MAX GAIN –30 DEC 1 TO DEC 6
14 17 0
–90
0 -0- 0-
MIN GAIN
9- 339
–40
433 04
–100
0
0.1 1 10 100 1000 1 10 100 1000 FREQUENCY (MHz) FREQUENCY (MHz)
Figure 14. AC Response Figure 17. Isolation in Transmit Disable Mode vs. Frequency
1.4 2.0 f = 10MHz 1.3 1.5 ) 1.2 1.0 B d 1.1 0.5 f = 5MHz 1.0 ROR (dB) 0 R f = 10MHz STEP SIZE ( T 0.9 –0.5 f = 42MHz TPU GAIN E OU 0.8 –1.0 f = 65MHz 0.7 –1.5 0.6
04339-0-015
–2.0
04339-0-018
0 6 12 18 24 30 36 42 48 54 60 0 6 12 18 24 30 36 42 48 54 60 GAIN CONTROL (Decimal Code) GAIN CONTROL (Decimal Code)
Figure 15. Output Step Size vs. Gain Control Figure 18. Gain Error vs. Gain Control for Various Frequencies Rev. C | Page 9 of 16 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS LOGIC INPUTS (TTL-/CMOS-COMPATIBLE LOGIC) TIMING REQUIREMENTS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TEST CIRCUIT APPLICATIONS INFORMATION GENERAL APPLICATIONS CIRCUIT DESCRIPTION GAIN PROGRAMMING FOR THE AD8324 INPUT BIAS, IMPEDANCE, AND TERMINATION OUTPUT BIAS, IMPEDANCE, AND TERMINATION POWER SUPPLY SIGNAL INTEGRITY LAYOUT CONSIDERATIONS INITIAL POWER-UP RAMP PIN AND BYP PIN FEATURES POWER SAVING FEATURES DISTORTION, ADJACENT CHANNEL POWER, AND DOCSIS UTILIZING DIPLEX FILTERS NOISE AND DOCSIS DIFFERENTIAL SIGNAL SOURCE DIFFERENTIAL SIGNAL FROM SINGLE-ENDED SOURCE SINGLE-ENDED SOURCE OUTLINE DIMENSIONS ORDERING GUIDE