Datasheet AD8488 (Analog Devices) - 7
| 制造商 | Analog Devices |
| 描述 | 128-Channel Digital X-Ray Analog Front End |
| 页数 / 页 | 20 / 7 — Data Sheet. AD8488. A1 BALL PAD CORNER. NOTE: E12 AND M12 ARE NC ON THE … |
| 修订版 | A |
| 文件格式/大小 | PDF / 359 Kb |
| 文件语言 | 英语 |
Data Sheet. AD8488. A1 BALL PAD CORNER. NOTE: E12 AND M12 ARE NC ON THE BGA BUT. MUST BE CONNECTED TO GROUND ON THE PCB. KEY. AVDD
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Data Sheet AD8488 A1 BALL PAD CORNER NOTE: E12 AND M12 ARE NC ON THE BGA BUT MUST BE CONNECTED TO GROUND ON THE PCB A B C D E F KEY G AVDD H AGND J DGND K DVDD L I/O M DIG I/O N NC P R T 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
003
BOTTOM VIEW
09801- Figure 3. 255-Ball CSP_BGA Ball Configuration (Bottom View)
Table 5. Pin Function Descriptions Mnemonic Pin No. I/O Description
AGND See Table 6 and Table 7 O Analog Power Ground (0 V). AVDD F6, F7, F8, F9, F10, G6, G11, H6, H11, H12, J6, I Analog Supply Voltage (5 V). J11, K6, K11, L6, L8, L9, L10, L11 CLK D15 I Clock for Mux Operation. CK_ENa E14 I Clock Gate for Channel 0 to Channel 63. CK_ENb F14 I Clock Gate for Channel 64 to Channel 127. CS_A N14 I Logic Level to Enable Channel 0 to Channel 63. CS_B M15 I Logic Level to Enable Channel 64 to Channel 127. CF1SEL0, B15, C15 I Binary Coded Logic Pins to Select One of Four Values of Integrator CF1SEL1 Capacitor CF1 (see Table 9). DGND F16, G15, G16, H15, H16, J15, J16, K15, K16, L16 O Digital Ground (0 V). DVDD B16, C16, D16, E16, F15, L15, M16, N16, P16, R16 I Power Supply for Digital Circuit (5 V). FSEL0, FSEL1 R14, T14 I Filter Time Constant Select (see Table 10). GNSEL0 to A14, B14, C14, D14 I Gain Select for the Gain Amp. Select one of four hold capacitors. The GNSEL3 four values are arranged in one of ten parallel options to establish ten gain values (see Table 11). GRST H14 I Gain Amp Reset. Closes the switch across Integrator Capacitor CF2 setting the output of the gain amplifier to zero. HOLD T16 I Gain Amp Hold. Connect the hold capacitor to the signal chain. Rev. A | Page 7 of 20 Document Outline Features Application General Description Functional Block Diagram Table of Contents Revision History Specifications Absolute Maximum Ratings Thermal Data Thermal Characterization ESD Caution Pin Configuration and Function Descriptions Signal Mnemonics Typical Performance Characteristics Theory of Operation Overview Analog Amplifier Troubleshooting Channels Timing Signals Timing Notes Applications Information Control Register Bit Maps Timing Diagrams Outline Dimensions Ordering Guide
Data Sheet AD8488 A1 BALL PAD CORNER NOTE: E12 AND M12 ARE NC ON THE BGA BUT MUST BE CONNECTED TO GROUND ON THE PCB A B C D E F KEY G AVDD H AGND J DGND K DVDD L I/O M DIG I/O N NC P R T 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
003
BOTTOM VIEW
09801- Figure 3. 255-Ball CSP_BGA Ball Configuration (Bottom View)
Table 5. Pin Function Descriptions Mnemonic Pin No. I/O Description
AGND See Table 6 and Table 7 O Analog Power Ground (0 V). AVDD F6, F7, F8, F9, F10, G6, G11, H6, H11, H12, J6, I Analog Supply Voltage (5 V). J11, K6, K11, L6, L8, L9, L10, L11 CLK D15 I Clock for Mux Operation. CK_ENa E14 I Clock Gate for Channel 0 to Channel 63. CK_ENb F14 I Clock Gate for Channel 64 to Channel 127. CS_A N14 I Logic Level to Enable Channel 0 to Channel 63. CS_B M15 I Logic Level to Enable Channel 64 to Channel 127. CF1SEL0, B15, C15 I Binary Coded Logic Pins to Select One of Four Values of Integrator CF1SEL1 Capacitor CF1 (see Table 9). DGND F16, G15, G16, H15, H16, J15, J16, K15, K16, L16 O Digital Ground (0 V). DVDD B16, C16, D16, E16, F15, L15, M16, N16, P16, R16 I Power Supply for Digital Circuit (5 V). FSEL0, FSEL1 R14, T14 I Filter Time Constant Select (see Table 10). GNSEL0 to A14, B14, C14, D14 I Gain Select for the Gain Amp. Select one of four hold capacitors. The GNSEL3 four values are arranged in one of ten parallel options to establish ten gain values (see Table 11). GRST H14 I Gain Amp Reset. Closes the switch across Integrator Capacitor CF2 setting the output of the gain amplifier to zero. HOLD T16 I Gain Amp Hold. Connect the hold capacitor to the signal chain. Rev. A | Page 7 of 20 Document Outline Features Application General Description Functional Block Diagram Table of Contents Revision History Specifications Absolute Maximum Ratings Thermal Data Thermal Characterization ESD Caution Pin Configuration and Function Descriptions Signal Mnemonics Typical Performance Characteristics Theory of Operation Overview Analog Amplifier Troubleshooting Channels Timing Signals Timing Notes Applications Information Control Register Bit Maps Timing Diagrams Outline Dimensions Ordering Guide