Datasheet ADSP-BF504 (Analog Devices) - 3

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ADSP-BF504 GENERAL DESCRIPTION
The ADSP-BF504 processors are members of the Blackfin® fam- reduction in power consumption, compared with just varying ily of products, incorporating the Analog Devices/Intel Micro the frequency of operation. This allows longer battery life for Signal Architecture (MSA). Blackfin processors combine a dual- portable appliances. MAC state-of-the-art signal processing engine, the advantages of a clean, orthogonal RISC-like microprocessor instruction set,
SYSTEM INTEGRATION
and single-instruction, multiple-data (SIMD) multimedia capa- The ADSP-BF504 processors are highly integrated system-on-a- bilities into a single instruction-set architecture. chip solutions for the next generation of embedded industrial, The ADSP-BF504 processors are completely code compatible instrumentation, and power/motion control applications. By with other Blackfin processors. ADSP-BF504 processors offer combining industry-standard interfaces with a high perfor- performance up to 400 MHz and reduced static power con- mance signal processing core, cost-effective applications can be sumption. The peripherals featured are shown in Table 1. developed quickly, without the need for costly external compo- nents. The system peripherals include a watchdog timer; two
Table 1. Processor Features
32-bit up/down counters with rotary support; eight 32-bit tim- ers/counters with PWM support; six pairs of 3-phase 16-bit
Feature ADSP-BF504
center-based PWM units; two dual-channel, full-duplex syn- Up/Down/Rotary Counters 2 chronous serial ports (SPORTs); two serial peripheral interface Timer/Counters with PWM 8 (SPI) compatible ports; two UARTs with IrDA® support; a par- allel peripheral interface (PPI); a removable storage interface 3-Phase PWM Units 2 (RSI) controller; an ACM controller; a controller area network SPORTs 2 (CAN) controller; and a 2-wire interface (TWI) controller. SPIs 2
PROCESSOR PERIPHERALS
UARTs 2 Parallel Peripheral Interface 1 The ADSP-BF504 processors contain a rich set of peripherals Removable Storage Interface 1 connected to the core via several high-bandwidth buses, provid- ing flexibility in system configuration as well as excellent overall CAN 1 system performance (see the block diagram on Page 1). These TWI 1 Blackfin processors contain high-speed serial and parallel ports, ADC Control Module (ACM) 1 an interrupt controller for flexible management of interrupts GPIOs 35 from the on-chip peripherals or external sources, and power management control functions to tailor the performance and ) L1 Instruction SRAM 16K power characteristics of the processor and system to many tes y L1 Instruction SRAM/Cache 16K application scenarios. (b y L1 Data SRAM 16K The SPORT, SPI, UART, PPI, and RSI peripherals are sup- L1 Data SRAM/Cache 16K ported by a flexible DMA structure. There are also separate L1 Scratchpad 4K Memor memory DMA channels dedicated to data transfers between the L3 Boot ROM 4K processor’s various memory spaces, including the boot ROM. Maximum Speed Grade1 400 MHz Multiple on-chip buses running at up to 100 MHz provide enough bandwidth to keep the processor core running along Maximum System Clock Speed 100 MHz with activity on all of the on-chip and external peripherals. Package Options 88-Lead LFCSP 1 The ADSP-BF504 processors include an interface to an off-chip For valid clock combinations, see Table 13, Table 14, Table 15, and Table 22. voltage regulator in support of the processor’s dynamic power By integrating a rich set of industry-leading system peripherals management capability. and memory, Blackfin processors are the platform of choice for
BLACKFIN PROCESSOR CORE
next-generation applications that require RISC-like program- mability, multimedia support, and leading-edge signal As shown in Figure 2, the Blackfin processor core contains two processing in one integrated package. 16-bit multipliers, two 40-bit accumulators, two 40-bit ALUs, four video ALUs, and a 40-bit shifter. The computation units
PORTABLE LOW-POWER ARCHITECTURE
process 8-, 16-, or 32-bit data from the register file. Blackfin processors provide world-class power management The compute register file contains eight 32-bit registers. When and performance. They are produced with a low power and low performing compute operations on 16-bit operand data, the voltage design methodology and feature on-chip dynamic register file operates as 16 independent 16-bit registers. All power management, which provides the ability to vary both the operands for compute operations come from the multiported voltage and frequency of operation to significantly lower overall register file and instruction constant fields. power consumption. This capability can result in a substantial Rev. C | Page 3 of 51 | June 2020 Document Outline Blackfin Embedded Processor Features Memory Peripherals Table of Contents Revision History General Description Portable Low-Power Architecture System Integration Processor Peripherals Blackfin Processor Core Memory Architecture Internal (Core-Accessible) Memory External (Interface-Accessible) Memory I/O Memory Space Booting Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) Event Control DMA Controllers Watchdog Timer Timers Up/Down Counters and Thumbwheel Interfaces 3-Phase PWM Units Serial Ports Serial Peripheral Interface (SPI) Ports UART Ports (UARTs) Parallel Peripheral Interface (PPI) General-Purpose Mode Descriptions ITU-R 656 Mode Descriptions RSI Interface Controller Area Network (CAN) Interface TWI Controller Interface Ports General-Purpose I/O (GPIO) Dynamic Power Management Full-On Operating Mode—Maximum Performance Active Operating Mode—Moderate Dynamic Power Savings Sleep Operating Mode—High Dynamic Power Savings Deep Sleep Operating Mode—Maximum Dynamic Power Savings Hibernate State—Maximum Static Power Savings Power Savings ADSP-BF504 Voltage Regulation Clock Signals Booting Modes Instruction Set Description Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) ACM Interface Additional Information Related Signal Chains Signal Descriptions Specifications Operating Conditions ADSP-BF504 Clock Related Operating Conditions Electrical Characteristics Total Power Dissipation Processor—Absolute Maximum Ratings ESD Sensitivity Processor—Timing Specifications Clock and Reset Timing Parallel Peripheral Interface Timing RSI Controller Timing Serial Ports Serial Peripheral Interface (SPI) Port—Master Timing Serial Peripheral Interface (SPI) Port—Slave Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing General-Purpose Port Timing Timer Cycle Timing Timer Clock Timing Up/Down Counter/Rotary Encoder Timing Pulse Width Modulator (PWM) Timing ADC Controller Module (ACM) Timing JTAG Test And Emulation Port Timing Processor—Output Drive Currents Processor—Test Conditions Output Enable Time Measurement Output Disable Time Measurement Example System Hold Time Calculation Capacitive Loading Processor—Environmental Conditions 88-Lead LFCSP Lead Assignment Outline Dimensions Ordering Guide