Datasheet ADSP-BF512, BF514, BF516, BF518 (Analog Devices) - 2
| 制造商 | Analog Devices |
| 描述 | Blackfin Embedded Processor |
| 页数 / 页 | 63 / 2 — ADSP-BF512. /BF514. /BF516. /BF518. TABLE OF CONTENTS. REVISION HISTORY. … |
| 修订版 | E |
| 文件格式/大小 | PDF / 2.5 Mb |
| 文件语言 | 英语 |
ADSP-BF512. /BF514. /BF516. /BF518. TABLE OF CONTENTS. REVISION HISTORY. 6/20—Rev. D to Rev. E
该数据表的模型线
- ADSP-BF512BBCZ-3 ADSP-BF512BBCZ-4 ADSP-BF512BSWZ-3 ADSP-BF512BSWZ-4 ADSP-BF512KBCZ-3 ADSP-BF512KBCZ-4 ADSP-BF512KSWZ-3 ADSP-BF512KSWZ-4
- ADSP-BF514BBCZ-3 ADSP-BF514BBCZ-4 ADSP-BF514BSWZ-3 ADSP-BF514BSWZ-4 ADSP-BF514KBCZ-3 ADSP-BF514KBCZ-4 ADSP-BF514KSWZ-3 ADSP-BF514KSWZ-4
文件文字版本
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ADSP-BF512 /BF514 /BF516 /BF518 TABLE OF CONTENTS
Features ... 1 Additional Information .. 16 Memory .. 1 Related Signal Chains ... 16 Peripherals ... 1 Signal Descriptions ... 17 Table of Contents ... 2 Specifications .. 20 Revision History .. 2 Operating Conditions ... 20 General Description ... 3 Electrical Characteristics ... 22 Portable Low Power Architecture ... 3 Absolute Maximum Ratings ... 25 System Integration .. 3 ESD Sensitivity ... 25 Blackfin Processor Core .. 3 Timing Specifications ... 26 Memory Architecture .. 5 Output Drive Currents ... 49 Event Handling .. 6 Test Conditions .. 51 DMA Controllers .. 6 Thermal Characteristics .. 55 Processor Peripherals ... 7 176-Lead LQFP_EP Lead Assignment ... 56 Lockbox Secure Technology Disclaimer ... 11 168-Ball CSP_BGA Ball Assignment ... 58 Dynamic Power Management .. 11 Outline Dimensions .. 60 Voltage Regulation Interface .. 12 Surface-Mount Design .. 61 Clock Signals ... 12 Automotive Products .. 62 Booting Modes ... 14 Ordering Guide ... 63 Instruction Set Description ... 15 Development Tools ... 15
REVISION HISTORY 6/20—Rev. D to Rev. E
This Rev E product data sheet removes the Flash Memory sec- tion, flash memory specifications, and all obsolete models that include 16M bit SPI flash memory. These changes are reflected in the following sections: Changes to Memory ... 1 Changes to Peripherals .. 1 Changes to Functional Block Diagram .. 1 Changes to Processor Comparison ... 3 Changes to Power Domains .. 12 Changes to Booting Modes ... 14 Changes to Signal Descriptions ... 17 Changes to Operating Conditions .. 20 Changes to Electrical Characteristics ... 22 Changes to 176-Lead LQFP_EP Lead Assignment .. 56 Changes to 168-Ball CSP_BGA Ball Assignment .. 58 Changes to Ordering Guide .. 63 Rev. E | Page 2 of 63 | June 2020 Document Outline Blackfin Embedded Processor Features Memory Peripherals Table of Contents Revision History General Description Portable Low Power Architecture System Integration Blackfin Processor Core Memory Architecture Internal (On-Chip) Memory External (Off-Chip) Memory One-Time Programmable Memory I/O Memory Space Booting from ROM Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) DMA Controllers Processor Peripherals Real-Time Clock Watchdog Timer Timers 3-Phase PWM General-Purpose (GP) Counter Serial Ports Serial Peripheral Interface (SPI) Ports UART Ports 2-Wire Interface (TWI) Removable Storage Interface (RSI) 10/100 Ethernet MAC IEEE 1588 Support Ports General-Purpose I/O (GPIO) Parallel Peripheral Interface (PPI) Code Security with Lockbox Secure Technology Lockbox Secure Technology Disclaimer Dynamic Power Management Full-On Operating Mode—Maximum Performance Active Operating Mode—Moderate Power Savings Sleep Operating Mode—High Dynamic Power Savings Deep Sleep Operating Mode—Maximum Dynamic Power Savings Hibernate State—Maximum Static Power Savings Power Savings Voltage Regulation Interface Clock Signals Booting Modes Instruction Set Description Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Signal Descriptions Specifications Operating Conditions Clock Related Operating Conditions Electrical Characteristics Total Power Dissipation Absolute Maximum Ratings ESD Sensitivity Timing Specifications Clock and Reset Timing Asynchronous Memory Read Cycle Timing Asynchronous Memory Write Cycle Timing SDRAM Interface Timing External DMA Request Timing Parallel Peripheral Interface Timing RSI Controller Timing Serial Ports Serial Peripheral Interface (SPI) Port—Master Timing Serial Peripheral Interface (SPI) Port—Slave Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing General-Purpose Port Timing Timer Clock Timing Timer Cycle Timing Up/Down Counter/Rotary Encoder Timing 10/100 Ethernet MAC Controller Timing JTAG Test And Emulation Port Timing Output Drive Currents Test Conditions Output Enable Time Measurement Output Disable Time Measurement Example System Hold Time Calculation Capacitive Loading Thermal Characteristics 176-Lead LQFP_EP Lead Assignment 168-Ball CSP_BGA Ball Assignment Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide
ADSP-BF512 /BF514 /BF516 /BF518 TABLE OF CONTENTS
Features ... 1 Additional Information .. 16 Memory .. 1 Related Signal Chains ... 16 Peripherals ... 1 Signal Descriptions ... 17 Table of Contents ... 2 Specifications .. 20 Revision History .. 2 Operating Conditions ... 20 General Description ... 3 Electrical Characteristics ... 22 Portable Low Power Architecture ... 3 Absolute Maximum Ratings ... 25 System Integration .. 3 ESD Sensitivity ... 25 Blackfin Processor Core .. 3 Timing Specifications ... 26 Memory Architecture .. 5 Output Drive Currents ... 49 Event Handling .. 6 Test Conditions .. 51 DMA Controllers .. 6 Thermal Characteristics .. 55 Processor Peripherals ... 7 176-Lead LQFP_EP Lead Assignment ... 56 Lockbox Secure Technology Disclaimer ... 11 168-Ball CSP_BGA Ball Assignment ... 58 Dynamic Power Management .. 11 Outline Dimensions .. 60 Voltage Regulation Interface .. 12 Surface-Mount Design .. 61 Clock Signals ... 12 Automotive Products .. 62 Booting Modes ... 14 Ordering Guide ... 63 Instruction Set Description ... 15 Development Tools ... 15
REVISION HISTORY 6/20—Rev. D to Rev. E
This Rev E product data sheet removes the Flash Memory sec- tion, flash memory specifications, and all obsolete models that include 16M bit SPI flash memory. These changes are reflected in the following sections: Changes to Memory ... 1 Changes to Peripherals .. 1 Changes to Functional Block Diagram .. 1 Changes to Processor Comparison ... 3 Changes to Power Domains .. 12 Changes to Booting Modes ... 14 Changes to Signal Descriptions ... 17 Changes to Operating Conditions .. 20 Changes to Electrical Characteristics ... 22 Changes to 176-Lead LQFP_EP Lead Assignment .. 56 Changes to 168-Ball CSP_BGA Ball Assignment .. 58 Changes to Ordering Guide .. 63 Rev. E | Page 2 of 63 | June 2020 Document Outline Blackfin Embedded Processor Features Memory Peripherals Table of Contents Revision History General Description Portable Low Power Architecture System Integration Blackfin Processor Core Memory Architecture Internal (On-Chip) Memory External (Off-Chip) Memory One-Time Programmable Memory I/O Memory Space Booting from ROM Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) DMA Controllers Processor Peripherals Real-Time Clock Watchdog Timer Timers 3-Phase PWM General-Purpose (GP) Counter Serial Ports Serial Peripheral Interface (SPI) Ports UART Ports 2-Wire Interface (TWI) Removable Storage Interface (RSI) 10/100 Ethernet MAC IEEE 1588 Support Ports General-Purpose I/O (GPIO) Parallel Peripheral Interface (PPI) Code Security with Lockbox Secure Technology Lockbox Secure Technology Disclaimer Dynamic Power Management Full-On Operating Mode—Maximum Performance Active Operating Mode—Moderate Power Savings Sleep Operating Mode—High Dynamic Power Savings Deep Sleep Operating Mode—Maximum Dynamic Power Savings Hibernate State—Maximum Static Power Savings Power Savings Voltage Regulation Interface Clock Signals Booting Modes Instruction Set Description Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Signal Descriptions Specifications Operating Conditions Clock Related Operating Conditions Electrical Characteristics Total Power Dissipation Absolute Maximum Ratings ESD Sensitivity Timing Specifications Clock and Reset Timing Asynchronous Memory Read Cycle Timing Asynchronous Memory Write Cycle Timing SDRAM Interface Timing External DMA Request Timing Parallel Peripheral Interface Timing RSI Controller Timing Serial Ports Serial Peripheral Interface (SPI) Port—Master Timing Serial Peripheral Interface (SPI) Port—Slave Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing General-Purpose Port Timing Timer Clock Timing Timer Cycle Timing Up/Down Counter/Rotary Encoder Timing 10/100 Ethernet MAC Controller Timing JTAG Test And Emulation Port Timing Output Drive Currents Test Conditions Output Enable Time Measurement Output Disable Time Measurement Example System Hold Time Calculation Capacitive Loading Thermal Characteristics 176-Lead LQFP_EP Lead Assignment 168-Ball CSP_BGA Ball Assignment Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide