Datasheet ADSP-BF512, BF514, BF516, BF518 (Analog Devices) - 10

ADSP-BF512 /BF514 /BF516 /BF518
• Programmable Ethernet event interrupt supports any com-
General-Purpose I/O (GPIO)
bination of: The ADSP-BF51x processors have 40 bidirectional, general- • Selected receive or transmit frame status conditions purpose I/O (GPIO) signals allocated across three separate • PHY interrupt condition GPIO modules—PORTFIO, PORTGIO, and PORTHIO, associ- ated with Port F, Port G, and Port H, respectively. Each • Wakeup frame detected GPIO-capable signal shares functionality with other peripherals • Selected MAC management counter(s) at half-full via a multiplexing scheme; however, the GPIO functionality is the default state of the device upon power-up. Neither GPIO • DMA descriptor error output nor input drivers are active by default. Each general-pur- • 47 MAC management statistics counters with selectable pose port signal can be individually controlled by manipulation clear-on-read behavior and programmable interrupts on of the port control, status, and interrupt registers. half maximum value
Parallel Peripheral Interface (PPI)
• Programmable receive address filters, including a 64-bin address hash table for multicast and/or unicast frames, and The ADSP-BF51x processors provide a parallel peripheral inter- programmable filter modes for broadcast, multicast, uni- face (PPI) that can connect directly to parallel analog-to-digital cast, control, and damaged frames and digital-to-analog converters, ITU-R-601/656 video encod- ers and decoders, and other general-purpose peripherals. The • Advanced power management supporting unattended PPI consists of a dedicated input clock signal, up to three frame transfer of receive and transmit frames and status to/from synchronization signals, and up to 16 data signals. external memory via DMA during low power sleep mode In ITU-R-656 modes, the PPI receives and parses a data stream • System wakeup from sleep operating mode upon magic of 8-bit or 10-bit data elements. On-chip decode of embedded packet or any of four user-definable wakeup frame filters preamble control and synchronization information • Support for 802.3Q tagged VLAN frames is supported. • Programmable MDC clock rate and preamble suppression Three distinct ITU-R-656 modes are supported: • In RMII operation, seven unused signals may be config- • Active video only mode—The PPI does not read in any ured as GPIO signals for other purposes data between the End of Active Video (EAV) and Start of Active Video (SAV) preamble symbols, or any data present
IEEE 1588 Support
during the vertical blanking intervals. In this mode, the The IEEE 1588 standard is a precision clock synchronization control byte sequences are not stored to memory; they are protocol for networked measurement and control systems. The filtered by the PPI. ADSP-BF518 processor includes hardware support for IEEE • Vertical blanking only mode—The PPI only transfers verti- 1588 with an integrated precision time protocol synchroniza- cal blanking interval (VBI) data, as well as horizontal tion engine (PTP_TSYNC). This engine provides hardware blanking information and control byte sequences on assisted time stamping to improve the accuracy of clock syn- VBI lines. chronization between PTP nodes. The main features of the PTP_SYNC engine are: • Entire field mode—The entire incoming bitstream is read in through the PPI. This includes active video, control pre- • Support for both IEEE 1588-2002 and IEEE 1588-2008 pro- amble sequences, and ancillary data that may be embedded tocol standards in horizontal and vertical blanking intervals. • Hardware assisted time stamping capable of up to 12.5 ns Though not explicitly supported, ITU-R-656 output functional- resolution ity can be achieved by setting up the entire frame structure • Lock adjustment (including active video, blanking, and control information) in • Programmable PTM message support memory and streaming the data out the PPI in a frame sync-less mode. The processor’s 2-D DMA features facilitate this transfer • Dedicated interrupts by allowing the static frame buffer (blanking and control codes) • Programmable alarm to be placed in memory once, and simply updating the active • Multiple input clock sources (SCLK, MII clock, external video information on a per-frame basis. clock) The general-purpose modes of the PPI are intended to suit a • Programmable pulse per second (PPS) output wide variety of data capture and transmission applications. The modes are divided into four main categories, each allowing up • Auxiliary snapshot to time stamp external events to 16 bits of data transfer per PPI_CLK cycle:
Ports
• Data receive with internally generated frame syncs Because of the rich set of peripherals, the processors group the • Data receive with externally generated frame syncs many peripheral signals to four ports—port F, port G, port H, • Data transmit with internally generated frame syncs and port J. Most of the associated pins/balls are shared by multi- ple signals. The ports function as multiplexer controls. • Data transmit with externally generated frame syncs Rev. E | Page 10 of 63 | June 2020 Document Outline Blackfin Embedded Processor Features Memory Peripherals Table of Contents Revision History General Description Portable Low Power Architecture System Integration Blackfin Processor Core Memory Architecture Internal (On-Chip) Memory External (Off-Chip) Memory One-Time Programmable Memory I/O Memory Space Booting from ROM Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) DMA Controllers Processor Peripherals Real-Time Clock Watchdog Timer Timers 3-Phase PWM General-Purpose (GP) Counter Serial Ports Serial Peripheral Interface (SPI) Ports UART Ports 2-Wire Interface (TWI) Removable Storage Interface (RSI) 10/100 Ethernet MAC IEEE 1588 Support Ports General-Purpose I/O (GPIO) Parallel Peripheral Interface (PPI) Code Security with Lockbox Secure Technology Lockbox Secure Technology Disclaimer Dynamic Power Management Full-On Operating Mode—Maximum Performance Active Operating Mode—Moderate Power Savings Sleep Operating Mode—High Dynamic Power Savings Deep Sleep Operating Mode—Maximum Dynamic Power Savings Hibernate State—Maximum Static Power Savings Power Savings Voltage Regulation Interface Clock Signals Booting Modes Instruction Set Description Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Signal Descriptions Specifications Operating Conditions Clock Related Operating Conditions Electrical Characteristics Total Power Dissipation Absolute Maximum Ratings ESD Sensitivity Timing Specifications Clock and Reset Timing Asynchronous Memory Read Cycle Timing Asynchronous Memory Write Cycle Timing SDRAM Interface Timing External DMA Request Timing Parallel Peripheral Interface Timing RSI Controller Timing Serial Ports Serial Peripheral Interface (SPI) Port—Master Timing Serial Peripheral Interface (SPI) Port—Slave Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing General-Purpose Port Timing Timer Clock Timing Timer Cycle Timing Up/Down Counter/Rotary Encoder Timing 10/100 Ethernet MAC Controller Timing JTAG Test And Emulation Port Timing Output Drive Currents Test Conditions Output Enable Time Measurement Output Disable Time Measurement Example System Hold Time Calculation Capacitive Loading Thermal Characteristics 176-Lead LQFP_EP Lead Assignment 168-Ball CSP_BGA Ball Assignment Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide