Datasheet ADSP-BF512, BF514, BF516, BF518 (Analog Devices) - 8

ADSP-BF512 /BF514 /BF516 /BF518
If configured to generate a hardware reset, the watchdog timer • Output polarity and clock gating control resets both the core and the processor peripherals. After a reset, • Dedicated asynchronous PWM shutdown signal software can determine if the watchdog was the source of the hardware reset by interrogating a status bit in the watchdog
General-Purpose (GP) Counter
timer control register. A 32-bit GP counter is provided that can sense 2-bit quadrature The timer is clocked by the system clock (SCLK) at a maximum or binary codes as typically emitted by industrial drives or man- frequency of fSCLK. ual thumb wheels. The counter can also operate in general-purpose up/down count modes. Then, count direction
Timers
is either controlled by a level-sensitive input signal or by two There are nine general-purpose programmable timer units in edge detectors. the ADSP-BF51x processors. Eight timers have an external sig- A third input can provide flexible zero marker support and can nal that can be configured either as a pulse width modulator alternatively be used to input the push-button signal of thumb (PWM) or timer output, as an input to clock the timer, or as a wheels. All three signals have a programmable debouncing mechanism for measuring pulse widths and periods of external circuit. events. These timers can be synchronized to an external clock input to the several other associated PF signals, an external An internal signal forwarded to the GP timer unit enables one clock input to the PPI_CLK input signal, or to the internal timer to measure the intervals between count events. Boundary SCLK. registers enable auto-zero operation or simple system warning by interrupts when programmable count values are exceeded. The timer units can be used in conjunction with the two UARTs to measure the width of the pulses in the data stream to provide
Serial Ports
a software auto-baud detect function for the respective serial The ADSP-BF51x processors incorporate two dual-channel syn- channels. chronous serial ports (SPORT0 and SPORT1) for serial and The timers can generate interrupts to the processor core provid- multiprocessor communications. The SPORTs support the fol- ing periodic events for synchronization, either to the system lowing features: clock or to a count of external signals. Serial port data can be automatically transferred to and from In addition to the eight general-purpose programmable timers, on-chip memory/external memory via dedicated DMA chan- a ninth timer is also provided. This extra timer is clocked by the nels. Each of the serial ports can work in conjunction with internal processor clock and is typically used as a system tick another serial port to provide TDM support. In this configura- clock for generation of operating system periodic interrupts. tion, one SPORT provides two transmit signals while the other SPORT provides the two receive signals. The frame sync and
3-Phase PWM
clock are shared. The processors integrate a flexible and programmable 3-phase Serial ports operate in five modes: PWM waveform generator that can be programmed to generate the required switching patterns to drive a 3-phase voltage • Standard DSP serial mode source inverter for ac induction (ACIM) or permanent magnet • Multichanne l (TDM) mode synchronous (PMSM) motor control. In addition, the PWM • I2S mode block contains special functions that considerably simplify the generation of the required PWM switching patterns for control • Packed I2S mode of the electronically commutated motor (ECM) or brushless dc • Left-justified mode motor (BDCM). Software can enable a special mode for switched reluctance motors (SRM).
Serial Peripheral Interface (SPI) Ports
Features of the 3-phase PWM generation unit are: The processors have two SPI-compatible ports (SPI0 and SPI1) that enable the processor to communicate with multiple SPI- • 16-bit center-based PWM generation unit compatible devices. • Programmable PWM pulse width The SPI interface uses three signals for transferring data: two • Single/double update modes data signals (master output-slave input–MOSI, and master • Programmable dead time and switching frequency input-slave output–MISO) and a clock signal (serial clock–SCK). An SPI chip select input signal (SPIxSS) lets other • Twos-complement implementation which permits smooth SPI devices select the processor, and multiple SPI chip select transition to full ON and full OFF states output signals let the processor select other SPI devices. The SPI • Possibility to synchronize the PWM generation to an exter- select signals are reconfigured general-purpose I/O signals. nal synchronization Using these signals, the SPI port provides a full-duplex, syn- • Special provisions for BDCM operation (crossover and chronous serial interface, which supports both master/slave output enable functions) modes and multimaster environments. • Wide variety of special switched reluctance (SR) operating modes Rev. E | Page 8 of 63 | June 2020 Document Outline Blackfin Embedded Processor Features Memory Peripherals Table of Contents Revision History General Description Portable Low Power Architecture System Integration Blackfin Processor Core Memory Architecture Internal (On-Chip) Memory External (Off-Chip) Memory One-Time Programmable Memory I/O Memory Space Booting from ROM Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) DMA Controllers Processor Peripherals Real-Time Clock Watchdog Timer Timers 3-Phase PWM General-Purpose (GP) Counter Serial Ports Serial Peripheral Interface (SPI) Ports UART Ports 2-Wire Interface (TWI) Removable Storage Interface (RSI) 10/100 Ethernet MAC IEEE 1588 Support Ports General-Purpose I/O (GPIO) Parallel Peripheral Interface (PPI) Code Security with Lockbox Secure Technology Lockbox Secure Technology Disclaimer Dynamic Power Management Full-On Operating Mode—Maximum Performance Active Operating Mode—Moderate Power Savings Sleep Operating Mode—High Dynamic Power Savings Deep Sleep Operating Mode—Maximum Dynamic Power Savings Hibernate State—Maximum Static Power Savings Power Savings Voltage Regulation Interface Clock Signals Booting Modes Instruction Set Description Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Signal Descriptions Specifications Operating Conditions Clock Related Operating Conditions Electrical Characteristics Total Power Dissipation Absolute Maximum Ratings ESD Sensitivity Timing Specifications Clock and Reset Timing Asynchronous Memory Read Cycle Timing Asynchronous Memory Write Cycle Timing SDRAM Interface Timing External DMA Request Timing Parallel Peripheral Interface Timing RSI Controller Timing Serial Ports Serial Peripheral Interface (SPI) Port—Master Timing Serial Peripheral Interface (SPI) Port—Slave Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing General-Purpose Port Timing Timer Clock Timing Timer Cycle Timing Up/Down Counter/Rotary Encoder Timing 10/100 Ethernet MAC Controller Timing JTAG Test And Emulation Port Timing Output Drive Currents Test Conditions Output Enable Time Measurement Output Disable Time Measurement Example System Hold Time Calculation Capacitive Loading Thermal Characteristics 176-Lead LQFP_EP Lead Assignment 168-Ball CSP_BGA Ball Assignment Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide