Datasheet ADSP-BF512, BF514, BF516, BF518 (Analog Devices) - 6

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ADSP-BF512 /BF514 /BF516 /BF518 I/O Memory Space Core Event Controller (CEC)
The processors do not define a separate I/O space. All resources The CEC supports nine general-purpose interrupts (IVG15–7), are mapped through the flat 32-bit address space. On-chip I/O in addition to the dedicated interrupt and exception events. Of devices have their control registers mapped into memory- these general-purpose interrupts, the two lowest priority mapped registers (MMRs) at addresses near the top of the interrupts (IVG15–14) are recommended to be reserved for 4G byte address space. These are separated into two smaller software interrupt handlers, leaving seven prioritized interrupt blocks, one which contains the control MMRs for all core func- inputs to support the peripherals of the processors. The inputs tions, and the other which contains the registers needed for to the CEC, identifies their names in the event vector table setup and control of the on-chip peripherals outside of the core. (EVT), and lists their priorities are described in the The MMRs are accessible only in supervisor mode and appear ADSP-BF51x Blackfin Processor Hardware Reference Manual as reserved space to on-chip peripherals. “System Interrupts” chapter.
Booting from ROM System Interrupt Controller (SIC)
The processors contain a small on-chip boot kernel, which con- The system interrupt controller provides the mapping and rout- figures the appropriate peripheral for booting. If the processors ing of events from the many peripheral interrupt sources to the are configured to boot from boot ROM memory space, the pro- prioritized general-purpose interrupt inputs of the CEC. cessor starts executing from the on-chip boot ROM. For more Although the processors provide a default mapping, the user information, see Booting Modes. can alter the mappings and priorities of interrupt events by writing the appropriate values into the interrupt assignment
EVENT HANDLING
registers (SIC_IARx). See the ADSP-BF51x Blackfin Processor The event controller handles all asynchronous and synchronous Hardware Reference Manual “System Interrupts” chapter for the events to the processor. The processors provide event handling inputs into the SIC and the default mappings into the CEC. that supports both nesting and prioritization. Nesting allows The SIC allows further control of event processing by providing multiple event service routines to be active simultaneously. three pairs of 32-bit interrupt control and status registers. Each Prioritization ensures that servicing of a higher priority event register contains a bit corresponding to each of the peripheral takes precedence over servicing of a lower priority event. interrupt events. For more information, see the ADSP-BF51x The controller provides support for five different types of Blackfin Processor Hardware Reference Manual “System Inter- events: rupts” chapter. • Emulation—An emulation event causes the processor to
DMA CONTROLLERS
enter emulation mode, allowing command and control of the processor through the JTAG interface. The ADSP-BF51x processors have multiple independent DMA channels that support automated data transfers with minimal • Reset—This event resets the processor. overhead for the processor core. DMA transfers can occur • Nonmaskable Interrupt (NMI)—The NMI event can be between the processor's internal memories and any of its DMA- generated by the software watchdog timer or by the NMI capable peripherals. Additionally, DMA transfers can be accom- input signal to the processor. The NMI event is frequently plished between any of the DMA-capable peripherals and used as a power-down indicator to initiate an orderly shut- external devices connected to the external memory interfaces, down of the system. including the SDRAM controller and the asynchronous mem- ory controller. DMA-capable peripherals include the Ethernet • Exceptions—Events that occur synchronously to program MAC, RSI, SPORTs, SPIs, UARTs, and PPI. Each individual flow; that is, the exception is taken before the instruction is DMA-capable peripheral has at least one dedicated DMA allowed to complete. Conditions such as data alignment channel. violations and undefined instructions cause exceptions. The processors’ DMA controller supports both one-dimen- • Interrupts—Events that occur asynchronously to program sional (1-D) and two-dimensional (2-D) DMA transfers. DMA flow. They are caused by input signals, timers, and other transfer initialization can be implemented from registers or peripherals, as well as by an explicit software instruction. from sets of parameters called descriptor blocks. Each event type has an associated register to hold the return The 2-D DMA capability supports arbitrary row and column address and an associated return-from-event instruction. When sizes up to 64K elements by 64K elements, and arbitrary row an event is triggered, the state of the processor is saved on the and column step sizes up to ±32K elements. Furthermore, the supervisor stack. column step size can be less than the row step size, allowing The event controller consists of two stages, the core event con- implementation of interleaved data streams. This feature is troller (CEC) and the system interrupt controller (SIC). The especially useful in video applications where data can be de- core event controller works with the system interrupt controller interleaved on the fly. to prioritize and control all system events. Conceptually, inter- rupts from the peripherals enter into the SIC, and are then routed directly into the general-purpose interrupts of the CEC. Rev. E | Page 6 of 63 | June 2020 Document Outline Blackfin Embedded Processor Features Memory Peripherals Table of Contents Revision History General Description Portable Low Power Architecture System Integration Blackfin Processor Core Memory Architecture Internal (On-Chip) Memory External (Off-Chip) Memory One-Time Programmable Memory I/O Memory Space Booting from ROM Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) DMA Controllers Processor Peripherals Real-Time Clock Watchdog Timer Timers 3-Phase PWM General-Purpose (GP) Counter Serial Ports Serial Peripheral Interface (SPI) Ports UART Ports 2-Wire Interface (TWI) Removable Storage Interface (RSI) 10/100 Ethernet MAC IEEE 1588 Support Ports General-Purpose I/O (GPIO) Parallel Peripheral Interface (PPI) Code Security with Lockbox Secure Technology Lockbox Secure Technology Disclaimer Dynamic Power Management Full-On Operating Mode—Maximum Performance Active Operating Mode—Moderate Power Savings Sleep Operating Mode—High Dynamic Power Savings Deep Sleep Operating Mode—Maximum Dynamic Power Savings Hibernate State—Maximum Static Power Savings Power Savings Voltage Regulation Interface Clock Signals Booting Modes Instruction Set Description Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Signal Descriptions Specifications Operating Conditions Clock Related Operating Conditions Electrical Characteristics Total Power Dissipation Absolute Maximum Ratings ESD Sensitivity Timing Specifications Clock and Reset Timing Asynchronous Memory Read Cycle Timing Asynchronous Memory Write Cycle Timing SDRAM Interface Timing External DMA Request Timing Parallel Peripheral Interface Timing RSI Controller Timing Serial Ports Serial Peripheral Interface (SPI) Port—Master Timing Serial Peripheral Interface (SPI) Port—Slave Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing General-Purpose Port Timing Timer Clock Timing Timer Cycle Timing Up/Down Counter/Rotary Encoder Timing 10/100 Ethernet MAC Controller Timing JTAG Test And Emulation Port Timing Output Drive Currents Test Conditions Output Enable Time Measurement Output Disable Time Measurement Example System Hold Time Calculation Capacitive Loading Thermal Characteristics 176-Lead LQFP_EP Lead Assignment 168-Ball CSP_BGA Ball Assignment Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide