Datasheet A17700 (Allegro) - 5
| 制造商 | Allegro |
| 描述 | Pressure Sensor Interface and Signal Conditioning IC with Polynomial Signal Compensation and Advanced Diagnostics |
| 页数 / 页 | 31 / 5 — Pressure Sensor Interface and Signal Conditioning IC. A17700. with … |
| 文件格式/大小 | PDF / 1.8 Mb |
| 文件语言 | 英语 |
Pressure Sensor Interface and Signal Conditioning IC. A17700. with Polynomial Signal Compensation and Advanced Diagnostics
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Pressure Sensor Interface and Signal Conditioning IC A17700 with Polynomial Signal Compensation and Advanced Diagnostics
VBRG VS 5 V VPU VBRG_2 VCC RPU CBYP CBRG VP 0.1 µF 0.1 µF
A17700
GND VBRGGND 0.1 µF (analog output) CL 1.8 nF (SENT/PWM output) VN OUT Device Output TEST1 VBRGGND_2 TEST2
Figure 2: Typical Application Circuit
Note: VBRG and VCC decoupling caps must be mounted as close as possible to device package. For increased ESD performances, connect NC (no connection) pins to GND. 5 Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com Document Outline Features and Benefits Description Package Functional Block Diagram Selection Guide Absolute Maximum Ratings Thermal Characteristics Pinout Diagram and Terminal List Operating Characteristics Functional Description Bandwidth Selection Output Response Time Power-On Time Front End Gain Adjustment Front End Differential Offset Adjustment Input Signal Range Calculation Fine Adjustment and Temperature Compensation Output Protocols Digital Output Mode Selection Digital Output Driver Fall Time Selection Broken Wire Detection Diagnostic Features Programming: Manchester Communication Entering Manchester Coding Manchester Interface Message Structure CRC Device Access Shadow Registers Device EEPROM and Register Access Lock EEPROM Map Volatile Registers Map Power Derating Package Outline Drawing
VBRG VS 5 V VPU VBRG_2 VCC RPU CBYP CBRG VP 0.1 µF 0.1 µF
A17700
GND VBRGGND 0.1 µF (analog output) CL 1.8 nF (SENT/PWM output) VN OUT Device Output TEST1 VBRGGND_2 TEST2
Figure 2: Typical Application Circuit
Note: VBRG and VCC decoupling caps must be mounted as close as possible to device package. For increased ESD performances, connect NC (no connection) pins to GND. 5 Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com Document Outline Features and Benefits Description Package Functional Block Diagram Selection Guide Absolute Maximum Ratings Thermal Characteristics Pinout Diagram and Terminal List Operating Characteristics Functional Description Bandwidth Selection Output Response Time Power-On Time Front End Gain Adjustment Front End Differential Offset Adjustment Input Signal Range Calculation Fine Adjustment and Temperature Compensation Output Protocols Digital Output Mode Selection Digital Output Driver Fall Time Selection Broken Wire Detection Diagnostic Features Programming: Manchester Communication Entering Manchester Coding Manchester Interface Message Structure CRC Device Access Shadow Registers Device EEPROM and Register Access Lock EEPROM Map Volatile Registers Map Power Derating Package Outline Drawing