Datasheet PMN50XP (NXP)
| 制造商 | NXP |
| 描述 | P-channel TrenchMOS extremely low level FET |
| 页数 / 页 | 11 / 1 — PMN50XP P-channel TrenchMOS extremely low level FET. Rev. 02 — 2 October … |
| 文件格式/大小 | PDF / 153 Kb |
| 文件语言 | 英语 |
PMN50XP P-channel TrenchMOS extremely low level FET. Rev. 02 — 2 October 2007. Product data sheet. Product profile
该数据表的模型线
文件文字版本
link to page 3 link to page 3 link to page 7 link to page 7 link to page 6 link to page 6
PMN50XP P-channel TrenchMOS extremely low level FET Rev. 02 — 2 October 2007 Product data sheet 1. Product profile 1.1 General description
Extremely low level P-channel enhancement mode Field-Effect Transistor (FET) in a plastic package. This product is designed and qualified for use in computing, communications, consumer and industrial applications only.
1.2 Features
Low on-state losses Low threshold voltage
1.3 Applications
Battery management Battery powered portable equipment Load Switching Low power DC to DC converters
1.4 Quick reference data Table 1. Quick reference Symbol Parameter Conditions Min Typ Max Unit
V ≥ ≤ DS drain-source voltage Tj 25 °C; Tj 150 °C - - -20 V ID drain current VGS = -4.5 V; Tsp = 25 °C; - - -4.8 A see Figure 1 and 3
Dynamic characteristics
QGD gate-drain charge VGS = -4.5 V; ID = -4.7 A; - 1.3 - nC VDS = -10 V; Tj = 25 °C; see Figure 9 and 10
Static characteristics
RDSon drain-source on-state VGS = -4.5 V; ID = -2.8 A; - 48 60 mΩ resistance Tj = 25 °C; see Figure 7 and 8 Document Outline 1. Product profile 1.1 General description 1.2 Features 1.3 Applications 1.4 Quick reference data 2. Pinning information 3. Ordering information 4. Limiting values 5. Thermal characteristics 6. Characteristics 7. Package outline 8. Revision history 9. Legal information 9.1 Data sheet status 9.2 Definitions 9.3 Disclaimers 9.4 Trademarks 10. Contact information 11. Contents
PMN50XP P-channel TrenchMOS extremely low level FET Rev. 02 — 2 October 2007 Product data sheet 1. Product profile 1.1 General description
Extremely low level P-channel enhancement mode Field-Effect Transistor (FET) in a plastic package. This product is designed and qualified for use in computing, communications, consumer and industrial applications only.
1.2 Features
Low on-state losses Low threshold voltage
1.3 Applications
Battery management Battery powered portable equipment Load Switching Low power DC to DC converters
1.4 Quick reference data Table 1. Quick reference Symbol Parameter Conditions Min Typ Max Unit
V ≥ ≤ DS drain-source voltage Tj 25 °C; Tj 150 °C - - -20 V ID drain current VGS = -4.5 V; Tsp = 25 °C; - - -4.8 A see Figure 1 and 3
Dynamic characteristics
QGD gate-drain charge VGS = -4.5 V; ID = -4.7 A; - 1.3 - nC VDS = -10 V; Tj = 25 °C; see Figure 9 and 10
Static characteristics
RDSon drain-source on-state VGS = -4.5 V; ID = -2.8 A; - 48 60 mΩ resistance Tj = 25 °C; see Figure 7 and 8 Document Outline 1. Product profile 1.1 General description 1.2 Features 1.3 Applications 1.4 Quick reference data 2. Pinning information 3. Ordering information 4. Limiting values 5. Thermal characteristics 6. Characteristics 7. Package outline 8. Revision history 9. Legal information 9.1 Data sheet status 9.2 Definitions 9.3 Disclaimers 9.4 Trademarks 10. Contact information 11. Contents