Datasheet TMP114 (Texas Instruments) - 7

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TMP114 www.ti.com
SNIS214 – JUNE 2021
6.6 I2C Interface Timing
minimum and maximum specifications are over –40 °C to 125 °C and VDD = 1.08 V to 1.98 V (unless otherwise noted)(1)
FAST MODE FAST MODE PLUS UNIT MIN MAX MIN MAX
f(SCL) SCL operating frequency 1 400 1 1000 kHz t(BUF) Bus-free time between STOP and START conditions 1.3 0.5 µs t(SUSTA) Repeated START condition setup time 0.6 0.26 µs Hold time after repeated START condition. t(HDSTA) 0 0 µs After this period, the first clock is generated. t(SUSTO) STOP condition setup time 0.6 0.26 µs t(HDDAT) Data hold time(2) 0 900 0 150 ns t(SUDAT) Data setup time 100 50 ns t(LOW) SCL clock low period 1.3 0.5 µs t(HIGH) SCL clock high period 0.6 0.26 µs t(VDAT) Data valid time (data response time)(3) 0.9 0.45 µs tR SDA, SCL rise time 20 300 120 ns
TION
20 x 20 x tF SDA, SCL fall time 300 120 ns (VDD / 5.5 V) (VDD / 5.5 V) ttimeout Timeout (SCL = SDA = GND) 20 30 20 30 ms
MA
tLPF Glitch suppression filter 50 50 ns
R
(1) The controller and device have the same VDD value. Values are based on statistical analysis of samples tested during initial release. (2) The maximum t(HDDAT) can be 0.9 µs for fast mode, and is less than the maximum t(VDAT) by a transition time. (3) t(VDAT) = time for data signal from SCL LOW to SDA output (HIGH to LOW, depending on which is worse).
6.7 Two-Wire Timing Diagram
t(LOW)
NCE INFO
t t R F t(HDSTA)
A V
SCL t t t t (HDSTA) (HIGH) (SUSTA) (SUSTO)
AD
t t (HDDAT) (SUDAT) SDA t(BUF) P S S P
Figure 6-1. Two-Wire Timing Diagram
Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: TMP114 Document Outline 1 Features 2 Applications 3 Description Table of Contents 4 Revision History 5 Pin Configuration and Functions 6 Specifications 6.1 Absolute Maximum Ratings 6.2 ESD Ratings 6.3 Recommended Operating Conditions 6.4 Thermal Information 6.5 Electrical Characteristics 6.6 I2C Interface Timing 6.7 Two-Wire Timing Diagram 7 Detailed Description 7.1 Overview 7.2 Functional Block Diagram 7.3 Feature Description 7.3.1 Cyclic Redundancy Check (CRC) 7.3.2 Temperature Limits 7.3.3 Slew Rate Warning 7.3.4 NIST Traceability 7.4 Device Functional Modes 7.4.1 Continuous Conversion Mode 7.4.2 Shutdown Mode 7.4.2.1 One-Shot Temperature Conversions 7.5 Programming 7.5.1 Temperature Data Format 7.5.2 I2C and SMBus Interface 7.5.3 Device Address 7.5.4 Bus Transactions 7.5.4.1 Auto-Increment 7.5.4.2 Writes 7.5.4.2.1 CRC Enabled Writes 7.5.4.3 Reads 7.5.4.3.1 CRC Enabled Reads 7.5.4.4 General Call Reset Function 7.5.4.5 Time-Out Function 7.5.4.6 I2C in I3C Mixed Fast Mode 7.5.4.7 Cyclic Redundancy Check Implementation 7.6 Register Map 8 Application and Implementation 8.1 Application Information 8.2 Typical Application 8.2.1 Design Requirements 8.2.2 Detailed Design Procedure 9 Power Supply Recommendations 10 Layout 10.1 Layout Guidelines 10.2 Layout Example 11 Device and Documentation Support 11.1 Receiving Notification of Documentation Updates 11.2 Support Resources 11.3 Trademarks 11.4 Electrostatic Discharge Caution 11.5 Glossary 12 Mechanical, Packaging, and Orderable Information 12.1 Tape and Reel Information