Datasheet GD32E507xx (GigaDevice) - 76
| 制造商 | GigaDevice |
| 描述 | Arm Cortex-M33 32-bit MCU |
| 页数 / 页 | 96 / 76 — 4.14. ADC characteristics. Table 4-29. ADC characteristics. Symbol. … |
| 文件格式/大小 | PDF / 2.8 Mb |
| 文件语言 | 英语 |
4.14. ADC characteristics. Table 4-29. ADC characteristics. Symbol. Parameter. Conditions. Min. Typ. Max Unit. Equation 1. Equation 1:
该数据表的模型线
文件文字版本
link to page 76 link to page 76 GD32E507xx Datasheet t (2) S_temp ADC sampling time when reading the temperature — — — μs (1) Based on characterization, not tested in production. (2) Shortest sampling time can be determined in the application by multiple iterations.
4.14. ADC characteristics Table 4-29. ADC characteristics Symbol Parameter Conditions Min Typ Max Unit
V (1) DDA Operating voltage — 1.71 3.3 3.6 V V (1) IN ADC input voltage range — 0 — VREF+ V V (2) REF+ Positive Reference Voltage — 1.8 — VDDA V Negative Reference V (2) REF- — — VSSA — V Voltage VDDA = 1.71 V to 2.4 V 0.1 — 14 MHz f (1) ADC ADC clock VDDA = 2.4 V to 3.6 V 0.1 — 35 MHz 12-bit 0.007 — 2.86 10-bit 0.008 — 3.33 MSP f (1) S Sampling rate 8-bit 0.01 — 4 S 6-bit 0.012 — 5 V (1) AIN Analog input voltage 16 external; 2 internal 0 — VDDA V R (2) AIN External input impedance See
Equation 1
— — 37.73 kΩ Input sampling switch R (2) ADC — — — 0.55 kΩ resistance No pin/pad capacitance C (2) ADC Input sampling capacitance — — 5.5 pF included t (2) CAL Calibration time fADC = 40 MHz — 3.275 — μs t (2) s Sampling time fADC = 40 MHz 0.0375 — 5.99 μs 12-bit — 14 — Total conversion 10-bit — 12 — 1/ t (2) CONV time(including sampling 8-bit — 10 — fADC time) 6-bit — 8 — t (2) SU Startup time — — — 1 μs (1) Based on characterization, not tested in production. (2) Guaranteed by design, not tested in production.
Equation 1:
RAIN max formula RAIN< Ts -R f ADC ADC*CADC* ln (2N+2) The formula above (Equation 1) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution).
Table 4-30. ADC RAIN max for fADC = 35 MHz Ts (cycles) ts (μs) RAIN max (kΩ)
1.5 0.0429 0.25 75 Document Outline Table of Contents List of Figures List of Tables 1. General description 2. Device overview 2.1. Device information 2.2. Block diagram 2.3. Pinouts and pin assignment 2.4. Memory map 2.5. Clock tree 2.6. Pin definitions 2.6.1. GD32E507Zx LQFP144 pin definitions 2.6.2. GD32E507Vx LQFP100 pin definitions 2.6.3. GD32E507Rx LQFP64 pin definitions 3. Functional description 3.1. Arm® Cortex®-M33 core 3.2. Embedded memory 3.3. Clock, reset and supply management 3.4. Boot modes 3.5. Power saving modes 3.6. Analog to digital converter (ADC) 3.7. Digital to analog converter (DAC) 3.8. DMA 3.9. General-purpose inputs/outputs (GPIOs) 3.10. Timers and PWM generation 3.11. Real time clock (RTC) 3.12. Inter-integrated circuit (I2C) 3.13. Serial peripheral interface (SPI) 3.14. Universal synchronous asynchronous receiver transmitter (USART) 3.15. Inter-IC sound (I2S) 3.16. Universal serial bus High-Speed interface (USBHS) 3.17. Controller area network (CAN) 3.18. Ethernet (ENET) 3.19. External memory controller (EXMC) 3.20. Comparators (CMP) 3.21. Trigonometric Math Unit (TMU) 3.22. Super High-Resolution Timer (SHRTIMER) 3.23. Serial/Quad Parallel Interface (SQPI) 3.24. Debug mode 3.25. Package and operation temperature 4. Electrical characteristics 4.1. Absolute maximum ratings 4.2. Operating conditions characteristics 4.3. Power consumption 4.4. EMC characteristics 4.5. Power supply supervisor characteristics 4.6. Electrical sensitivity 4.7. External clock characteristics 4.8. Internal clock characteristics 4.9. PLL characteristics 4.10. Memory characteristics 4.11. NRST pin characteristics 4.12. GPIO characteristics 4.13. Temperature sensor characteristics 4.14. ADC characteristics 4.15. DAC characteristics 4.16. Comparators characteristics 4.17. Trigonometric Math Unit (TMU) characteristics 4.18. I2C characteristics 4.19. SPI characteristics 4.20. I2S characteristics 4.21. USART characteristics 4.22. CAN characteristics 4.23. USBHS characteristics 4.24. EXMC characteristics 4.25. Serial/Quad Parallel Interface (SQPI) characteristics 4.26. Super High-Resolution Timer (SHRTIMER) characteristics 4.27. TIMER characteristics 4.28. WDGT characteristics 4.29. Parameter condition 5. Package information 5.1. LQFP144 package outline dimensions 5.2. LQFP100 package outline dimensions 5.3. LQFP64 package outline dimensions 6. Ordering information 7. Revision history
4.14. ADC characteristics Table 4-29. ADC characteristics Symbol Parameter Conditions Min Typ Max Unit
V (1) DDA Operating voltage — 1.71 3.3 3.6 V V (1) IN ADC input voltage range — 0 — VREF+ V V (2) REF+ Positive Reference Voltage — 1.8 — VDDA V Negative Reference V (2) REF- — — VSSA — V Voltage VDDA = 1.71 V to 2.4 V 0.1 — 14 MHz f (1) ADC ADC clock VDDA = 2.4 V to 3.6 V 0.1 — 35 MHz 12-bit 0.007 — 2.86 10-bit 0.008 — 3.33 MSP f (1) S Sampling rate 8-bit 0.01 — 4 S 6-bit 0.012 — 5 V (1) AIN Analog input voltage 16 external; 2 internal 0 — VDDA V R (2) AIN External input impedance See
Equation 1
— — 37.73 kΩ Input sampling switch R (2) ADC — — — 0.55 kΩ resistance No pin/pad capacitance C (2) ADC Input sampling capacitance — — 5.5 pF included t (2) CAL Calibration time fADC = 40 MHz — 3.275 — μs t (2) s Sampling time fADC = 40 MHz 0.0375 — 5.99 μs 12-bit — 14 — Total conversion 10-bit — 12 — 1/ t (2) CONV time(including sampling 8-bit — 10 — fADC time) 6-bit — 8 — t (2) SU Startup time — — — 1 μs (1) Based on characterization, not tested in production. (2) Guaranteed by design, not tested in production.
Equation 1:
RAIN max formula RAIN< Ts -R f ADC ADC*CADC* ln (2N+2) The formula above (Equation 1) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution).
Table 4-30. ADC RAIN max for fADC = 35 MHz Ts (cycles) ts (μs) RAIN max (kΩ)
1.5 0.0429 0.25 75 Document Outline Table of Contents List of Figures List of Tables 1. General description 2. Device overview 2.1. Device information 2.2. Block diagram 2.3. Pinouts and pin assignment 2.4. Memory map 2.5. Clock tree 2.6. Pin definitions 2.6.1. GD32E507Zx LQFP144 pin definitions 2.6.2. GD32E507Vx LQFP100 pin definitions 2.6.3. GD32E507Rx LQFP64 pin definitions 3. Functional description 3.1. Arm® Cortex®-M33 core 3.2. Embedded memory 3.3. Clock, reset and supply management 3.4. Boot modes 3.5. Power saving modes 3.6. Analog to digital converter (ADC) 3.7. Digital to analog converter (DAC) 3.8. DMA 3.9. General-purpose inputs/outputs (GPIOs) 3.10. Timers and PWM generation 3.11. Real time clock (RTC) 3.12. Inter-integrated circuit (I2C) 3.13. Serial peripheral interface (SPI) 3.14. Universal synchronous asynchronous receiver transmitter (USART) 3.15. Inter-IC sound (I2S) 3.16. Universal serial bus High-Speed interface (USBHS) 3.17. Controller area network (CAN) 3.18. Ethernet (ENET) 3.19. External memory controller (EXMC) 3.20. Comparators (CMP) 3.21. Trigonometric Math Unit (TMU) 3.22. Super High-Resolution Timer (SHRTIMER) 3.23. Serial/Quad Parallel Interface (SQPI) 3.24. Debug mode 3.25. Package and operation temperature 4. Electrical characteristics 4.1. Absolute maximum ratings 4.2. Operating conditions characteristics 4.3. Power consumption 4.4. EMC characteristics 4.5. Power supply supervisor characteristics 4.6. Electrical sensitivity 4.7. External clock characteristics 4.8. Internal clock characteristics 4.9. PLL characteristics 4.10. Memory characteristics 4.11. NRST pin characteristics 4.12. GPIO characteristics 4.13. Temperature sensor characteristics 4.14. ADC characteristics 4.15. DAC characteristics 4.16. Comparators characteristics 4.17. Trigonometric Math Unit (TMU) characteristics 4.18. I2C characteristics 4.19. SPI characteristics 4.20. I2S characteristics 4.21. USART characteristics 4.22. CAN characteristics 4.23. USBHS characteristics 4.24. EXMC characteristics 4.25. Serial/Quad Parallel Interface (SQPI) characteristics 4.26. Super High-Resolution Timer (SHRTIMER) characteristics 4.27. TIMER characteristics 4.28. WDGT characteristics 4.29. Parameter condition 5. Package information 5.1. LQFP144 package outline dimensions 5.2. LQFP100 package outline dimensions 5.3. LQFP64 package outline dimensions 6. Ordering information 7. Revision history