Datasheet RAA227063 (Renesas)

Datasheet RAA227063 4.5V to 60V 3-Phase Smart Gate Driver The RAA227063 is a smart gate driver IC for 3-phase
Features
Brushless DC (BLDC) motor applications. It ▪ Wide V integrates three half-bridge smart gate drivers that are IN range: 4.5V to 60V (65V abs max) capable of driving up to three N-channel MOSFET ▪ Switching frequency range up to 200kHz bridges and supports bridge voltages from 4.5V to ▪ 3-Phase drive for BLDC application 60V. Each gate driver supports up to 1A source and • Peak 1A/2A source/sink current with 2A sink peak drive current with programmable drive programmable drive strength strength control. Adjustable and adaptive dead-times • Supports 8 adjustable levels of drive strength are implemented to ensure robustness and flexibility. through hardware interface and 16 adjustable The active gate holding mechanism prevents a Miller levels of drive strength through SPI interface effect-induced cross-conduction and further enhances robustness. ▪ Adaptive and adjustable dead time ▪ Fully integrated power supply architecture The device integrates power supplies that power internal analog and logic circuitry, high-side and • Two VCC LDOs allow for Sleep mode low IQ low-side drivers, and a dedicated supply for powering • 500mA buck-boost switching regulator external microcontrollers. The device also features a generates drive voltage (5V to 15V adjustable) low-power Sleep mode that consumes only 20µA to • 200mA adjustable output LDO for MCU supplies maximize battery life in portable applications. ▪ Flexible configuration The driver control inputs can be configured to either • 3-phase HI/LI mode and 3-phase PWM mode 3-phase LI/HI or 3-phase PWM modes. Three • Support half-bridge, full-bridge configuration accurate differential amplifiers with adjustable gain ▪ Three current sense amplifiers are integrated to support ground-side shunt current sensing or low-side r • Four levels of sense gain setting DS(ON) current sensing for each bridge. The device can also support sensorless • Supports DC offset calibration during power-up operation using back EMF in brushless DC motors. and on-the-fly The device can be configured to use either a • Supports both ground-side shunt sense or hardware interface or SPI interface. For hardware low-side MOSFET rDS(ON) sense interface configuration, key driver operating ▪ Back-EMF sensing for BLDC sensorless operation parameters can be set using resistor pin-straps. For ▪ Features both hardware interface and SPI interface SPI configuration, all the parameters can be set ▪ Extensive fault protection functions (VCC UV, VM/ through the SPI Bus, which allows better monitoring. VBRIDGE UV, charge pump UV, MOSFET VDS Extensive protection functions include bridge voltage OCP, current sense OCP, thermal UV protection, buck-boost OV/UV/OC protection, warning/shutdown, buck-boost current limiting, charge pump UV protection, MOSFET drain-to- buck-boost OCP, buck-boost UV/OV) source voltage OC protection, current sense ▪ Supports reverse battery protection by additional overcurrent protection, thermal warning, and external circuitry shutdown. Fault conditions are indicated on a ▪ 7mm x 7mm 48 Ld QFN package (0.5mm pitch) dedicated nFAULT pin and in SPI status registers.
Applications
▪ Power tools, fans, pumps, E-bikes ▪ Industrial automation, robotics, drones R16DS0045EU0101 Rev.1.01 Page 1 Nov 29, 2021 © 2021 Renesas Electronics Document Outline Applications Features Contents 1. Overview 1.1 Typical Application Circuits 2. Pin Information 2.1 Pin Assignments 2.2 Pin Descriptions 3. Specifications 3.1 Absolute Maximum Ratings 3.2 Thermal Information 3.3 Recommended Operating Conditions 3.4 Electrical Specifications 4. Typical Performance Curves 5. Functional Description 5.1 Modes of Operation and Power-On Sequence 5.1.1 Definitions of State of Different Modes 5.1.2 Mode Transition 5.1.3 Modes of Operation 5.1.3.1 Gate Driver Control Modes 5.1.3.2 3-phase HI/LI Mode 5.1.3.3 3-phase PWM Mode 5.1.4 Gate Driver Structure and Feature 5.1.4.1 Driver Structure 5.1.4.2 Adjustable Slew-Rate 5.1.4.3 Driver Robustness Enhancement 5.1.4.4 Gate Drive Diagram 5.1.4.5 Gate Drive Scheme in 3-phase HI/LI Mode 5.1.5 Power Architecture 5.1.5.1 Power Architecture Overview 5.1.5.2 Low-Side Driver Supply (VDRV) 5.1.5.3 Charge Pump 5.1.5.4 VCC Supply 5.1.5.5 MCU AUXVCC Supply 5.1.6 Power-On Sequence 5.2 Fault Management 5.2.1 Fault Conditions Types 5.2.2 nFAULT Indicator 5.3 Current Sensing and BEMF Sensing 5.3.1 Overview 5.3.2 Details on Different Sensing Configurations 5.3.2.1 Configuration 1 5.3.2.2 Configuration 2 5.3.2.3 Configuration 3 5.3.2.4 Configuration 4 5.3.2.5 Configuration 5 5.3.2.6 Configuration 6 5.3.2.7 Configuration 7 5.3.2.8 Configuration 8 5.3.2.9 Configuration 9 5.3.3 Structure of Amplifiers CSA, CSB, and CSC 5.3.4 BEMF Sensing Control Signal Logic 5.3.5 Multiplexer Control Signal Logic 5.3.6 Sample and Hold Timing Logic 5.3.7 Low-Side rDS(ON) Current Sensing Timing Logic 5.4 Hardware Interface for Parameter Setting 5.4.1 Parameter Setting Tables 5.5 Serial Peripheral Interface (SPI) 5.5.1 Communication Protocol 5.5.2 Timing Diagram 6. Register Map 7. Package Outline Drawing 8. Ordering Information 9. Revision History