Datasheet ADGS1414D (Analog Devices) - 9

link to page 10 link to page 10
Data Sheet ADGS1414D CONTINUOUS CURRENT PER CHANNEL, Sx OR Dx Table 4. Eight Channels On Parameter 25°C 85°C 125°C Unit
CONTINUOUS CURRENT, Sx OR Dx1 VDD = +15 V, VSS = −15 V (θJA = 65.5°C/W) 273 156 80 mA maximum VDD = +12 V, VSS = 0 V (θJA = 65.5°C/W) 221 133 72 mA maximum VDD = +5 V, VSS = −5 V (θJA = 65.5°C/W) 206 126 70 mA maximum 1 Sx refers to the S1 to S8 pins, and Dx refers to the D1 to D8 pins.
Table 5. One Channel On Parameter 25°C 85°C 125°C Unit
CONTINUOUS CURRENT, Sx OR Dx1 VDD = +15 V, VSS = −15 V (θJA = 65.5°C/W) 490 225 87 mA maximum VDD = +12 V, VSS = 0 V (θJA = 65.5°C/W) 399 200 84 mA maximum VDD = +5 V, VSS = −5 V (θJA = 65.5°C/W) 373 192 83 mA maximum 1 Sx refers to the S1 to S8 pins, and Dx refers to the D1 to D8 pins.
TIMING CHARACTERISTICS
VL = 2.7 V to 5.5 V, GND = 0 V, and al specifications minimum temperature (TMIN) to maximum temperature (TMAX), unless otherwise noted. Guaranteed by design and characterization, not production tested. See Figure 2 to Figure 4 for the timing diagrams.
Table 6. Parameter Limit Unit Test Conditions/Comments
TIMING CHARACTERISTICS t1 20 ns min SCLK period t2 8 ns min SCLK high pulse width t3 8 ns min SCLK low pulse width t4 10 ns min CS falling edge to SCLK active edge t5 6 ns min Data setup time t6 8 ns min Data hold time t7 10 ns min SCLK active edge to CS rising edge t8 20 ns max CS falling edge to SDO data available t 1 9 30 ns max SCLK falling edge to SDO data available t10 30 ns max CS rising edge to SDO returns to high t11 20 ns min CS high time between SPI commands t12 8 ns min CS falling edge to SCLK becomes stable t13 8 ns min CS rising edge to SCLK becomes stable 1 Measured with a 20 pF load. t9 determines the maximum SCLK frequency when SDO is used. Rev. 0 | Page 9 of 28 Document Outline Features Applications General Description Functional Block Diagram Product Highlights Revision History Specifications ±15 V Dual Supply ±5 V Dual Supply 12 V Single Supply Continuous Current per Channel, Sx or Dx Timing Characteristics Timing Diagrams Absolute Maximum Ratings Thermal Resistance Electrostatic Discharge (ESD) Ratings ESD Ratings for ADGS1414D ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Test Circuits Terminology Theory of Operation Address Mode Error Detection Features Cyclic Redundancy Check (CRC) Error Detection SCLK Count Error Detection Invalid Read and Write Address Error Clearing the Error Flags Register Burst Mode Software Reset Daisy-Chain Mode Power-On Reset Applications Information System Channel Density Route Through Pins Integrated Passive Components Break-Before-Make Switching Digital Input Buffers Power Supply Rails Power Supply Recommendations 1.8 V Logic Compatibility Register Summary Register Details Switch Data Register Error Configuration Register Error Flags Register Burst Enable Register Software Reset Register Outline Dimensions Ordering Guide