Datasheet ADGS1414D (Analog Devices) - 10

ADGS1414D Data Sheet Timing Diagrams t1 SCLK t2 t t t7 4 3 CS t t 6 5 SDI R/W A6 A5 D2 D1 D0 t t 9 10 SDO 0 0 1 D2 D1 D0
002
t8
23895- Figure 2. Address Mode Timing Diagram
t1 SCLK t t 3 2 t4 t7 CS t t 6 5 SDI D7 D6 D0 D7 D6 D1 D0 INPUT BYTE FOR DEVICE N INPUT BYTE FOR DEVICE N + 1 t t10 9 SDO 0 0 0 D7 D6 D1 D0
003
ZERO BYTE INPUT BYTE FOR DEVICE N t8
23895- Figure 3. Daisy-Chain Timing Diagram
t11 CS SCLK
004
t13 t12
23895- Figure 4. SCLK and CS Timing Relationship Rev. 0 | Page 10 of 28 Document Outline Features Applications General Description Functional Block Diagram Product Highlights Revision History Specifications ±15 V Dual Supply ±5 V Dual Supply 12 V Single Supply Continuous Current per Channel, Sx or Dx Timing Characteristics Timing Diagrams Absolute Maximum Ratings Thermal Resistance Electrostatic Discharge (ESD) Ratings ESD Ratings for ADGS1414D ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Test Circuits Terminology Theory of Operation Address Mode Error Detection Features Cyclic Redundancy Check (CRC) Error Detection SCLK Count Error Detection Invalid Read and Write Address Error Clearing the Error Flags Register Burst Mode Software Reset Daisy-Chain Mode Power-On Reset Applications Information System Channel Density Route Through Pins Integrated Passive Components Break-Before-Make Switching Digital Input Buffers Power Supply Rails Power Supply Recommendations 1.8 V Logic Compatibility Register Summary Register Details Switch Data Register Error Configuration Register Error Flags Register Burst Enable Register Software Reset Register Outline Dimensions Ordering Guide