Datasheet ADG611, ADG612, ADG613 (Analog Devices) - 3

制造商Analog Devices
描述1 pC Charge Injection, 100 pA Leakage, CMOS, ±5 V/+5 V/+3 V, Quad SPST Switches
页数 / 页16 / 3 — ADG611/ADG612/ADG613. SPECIFICATIONS DUAL-SUPPLY OPERATION. Table 1. …
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ADG611/ADG612/ADG613. SPECIFICATIONS DUAL-SUPPLY OPERATION. Table 1. Parameter. +25°C. −40°C to +85°C. −40°C to +125°C1. Unit

ADG611/ADG612/ADG613 SPECIFICATIONS DUAL-SUPPLY OPERATION Table 1 Parameter +25°C −40°C to +85°C −40°C to +125°C1 Unit

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ADG611/ADG612/ADG613 SPECIFICATIONS DUAL-SUPPLY OPERATION
VDD = +5 V ± 10%, VSS = −5 V ± 10%, GND = 0 V, unless otherwise noted.
Table 1. Parameter +25°C −40°C to +85°C −40°C to +125°C1 Unit Test Conditions/Comments
ANALOG SWITCH Analog Signal Range VSS to VDD V On Resistance, RON 85 Ω typ VS = ±3 V, IS = −1 mA; see Figure 14 115 140 160 Ω max VS = ±3 V, IS = −1 mA; see Figure 14 On-Resistance Match 2 Ω typ VS = ±3 V, IS = −1 mA Between Channels, ΔRON 4 5.5 6.5 Ω max VS = ±3 V, IS = −1 mA On-Resistance Flatness, RFLAT(ON) 25 Ω typ VS = ±3 V, IS = −1 mA 40 55 60 Ω max VS = ±3 V, IS = −1 mA LEAKAGE CURRENTS VDD = +5.5 V, VSS = −5.5 V Source Off Leakage, IS(OFF) ±0.01 nA typ VD = ±4.5 V, VS = +4.5 V; see Figure 15 ±0.1 ±0.25 ±2 nA max VD = ±4.5 V, VS = +4.5 V; see Figure 15 Drain Off Leakage, ID(OFF) ±0.01 nA typ VD = ±4.5 V, VS = + 4.5 V; see Figure 15 ±0.1 ±0.25 ±2 nA max VD = ±4.5 V, VS = + 4.5 V; see Figure 15 Channel On Leakage, ID(ON), IS(ON) ±0.01 nA typ VD = VS = ±4.5 V; see Figure 16 ±0.1 ± 0.25 ± 6 nA max VD = VS = ±4.5 V; see Figure 16 DIGITAL INPUTS Input High Voltage, VINH 2.4 V min Input Low Voltage, VINL 0.8 V max Input Current, IINL or IINH 0.005 μA typ VIN = VINL or VINH ±0.1 μA max VIN = VINL or VINH Digital Input Capacitance, CIN 2 pF typ DYNAMIC CHARACTERISTICS2 tON 45 ns typ RL = 300 Ω, CL = 35 pF, VS = 3.0 V; see Figure 17 65 75 90 ns max RL = 300 Ω, CL = 35 pF, VS = 3.0 V; see Figure 17 tOFF 25 ns typ RL = 300 Ω, CL = 35 pF, VS = 3.0 V; see Figure 17 40 45 50 ns max RL = 300 Ω, CL = 35 pF, VS = 3.0 V; see Figure 17 Break-Before-Make Time Delay, tBBM 15 ns typ RL = 300 Ω, CL = 35 pF, VS1 = VS2 = 3.0 V; see Figure 18 10 ns min RL = 300 Ω, CL = 35 pF, VS1 = VS2 = 3.0 V; see Figure 18 Charge Injection −0.5 pC typ VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 19 Off Isolation −65 dB typ RL = 50 Ω, CL = 5 pF, f = 10 MHz; see Figure 20 Channel-to-Channel Crosstalk −90 dB typ RL = 50 Ω, CL = 5 pF, f = 10 MHz; see Figure 21 −3 dB Bandwidth 680 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 22 CS(OFF) 5 pF typ f = 1 MHz CD(OFF) 5 pF typ f = 1 MHz CD(ON), CS(ON) 5 pF typ f = 1 MHz POWER REQUIREMENTS VDD = +5.5 V, VSS = −5.5 V IDD 0.001 μA typ Digital inputs = 0 V or 5.5 V 1.0 μA max Digital inputs = 0 V or 5.5 V ISS 0.001 μA typ Digital inputs = 0 V or 5.5 V 1.0 μA max Digital inputs = 0 V or 5.5 V 1 The temperature range for the Y version is −40°C to +125°C. 2 Guaranteed by design; not subject to production test. Rev. A | Page 3 of 16 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DUAL-SUPPLY OPERATION SINGLE-SUPPLY OPERATION ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY TEST CIRCUITS APPLICATIONS INFORMATION OUTLINE DIMENSIONS ORDERING GUIDE