Datasheet ADG619, ADG620 (Analog Devices) - 10

ADG619/ADG620 TERMINOLOGY IDD CD, CS (On)
Positive supply current. On switch capacitance.
ISS tON
Negative supply current. Delay between applying the digital control input and the output switching on.
RON
Ohmic resistance between D and S terminals.
tOFF
Delay between applying the digital control input and the output
ΔRON
switching off. On resistance match between any two channels.
tMBB RFLAT (ON)
On time is measured between the 80% points of both switches, Flatness is defined as the difference between the maximum and when switching from one address state to another. minimum value of on resistance as measured over the specified analog signal range.
tBBM
Off time or on time is measured between the 90% points of
IS (Off)
both switches, when switching from one address state Source leakage current with the switch off. to another.
ID, IS (On) Charge Injection
Channel leakage current with the switch on. A measure of the glitch impulse transferred from the digital
V
input to the analog output during switching.
D, VS
Analog voltage on Terminal D and Terminal S.
Crosstalk V
A measure of unwanted signal coupled through from one
INL
Maximum input voltage for Logic 0. channel to another as a result of parasitic capacitance.
V Off Isolation INH
Minimum input voltage for Logic 1. A measure of unwanted signal coupling through an off switch.
I Bandwidth INL, IINH
Input current of the digital input. The frequency response of the on switch.
C Insertion Loss S (Off )
Off switch source capacitance. The loss due to the on resistance of the switch. Rev. C | Page 10 of 16 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DUAL SUPPLY SINGLE SUPPLY ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY TEST CIRCUITS OUTLINE DIMENSIONS ORDERING GUIDE