Datasheet ADG714, ADG715 (Analog Devices)
| 制造商 | Analog Devices |
| 描述 | CMOS, Low Voltage Serially Controlled, Octal SPST Switches |
| 页数 / 页 | 21 / 1 — CMOS, Low Voltage. Serially Controlled, Octal SPST Switches. Data Sheet. … |
| 修订版 | E |
| 文件格式/大小 | PDF / 368 Kb |
| 文件语言 | 英语 |
CMOS, Low Voltage. Serially Controlled, Octal SPST Switches. Data Sheet. ADG714/. ADG715. FEATURES. FUNCTIONAL BLOCK DIAGRAMS
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CMOS, Low Voltage Serially Controlled, Octal SPST Switches Data Sheet ADG714/ ADG715 FEATURES FUNCTIONAL BLOCK DIAGRAMS SPI/QSPI/MICROWIRE-compatible interface (ADG714) ADG714 ADG715: I2C-compatible interface (ADG715) S1 D1 2.7 V to 5.5 V single supply S2 D2 ±2.5 V dual supply S3 D3 2.5 Ω on resistance S4 D4 0.6 Ω on resistance flatness S5 D5 0.1 nA leakage currents S6 D6 Octal SPST S7 D7 S8 D8 Power-on reset Fast switching times INPUT SHIFT DOUT REGISTER TTL/CMOS compatible 24-lead TSSOP and 24-lead LFCSP
001
SCLK DIN SYNC RESET APPLICATIONS
00043- Figure 1. ADG714 Functional Block Diagram
Data acquisition systems Communication systems ADG715 Relay replacement S1 D1 Audio and video switching S2 D2 S3 D3 GENERAL DESCRIPTION S4 D4
The ADG714/ADG715 are complementary metal-oxide
S5 D5 S6 D6
semiconductor (CMOS), octal single-pole, single-throw (SPST)
S7 D7
switches, controlled via either a 2- or 3-wire serial interface. On
S8 D8
resistance is closely matched between the switches and is flat
INTERFACE
over the full signal range. Each switch conducts equally well in
LOGIC
both directions, and the input signal range extends to the
RESET
002 supplies. Data is written to these devices in the form of 8 bits,
SDA SCL A0 A1
00043- each bit corresponding to one channel. Figure 2. ADG715 Functional Block Diagram The ADG714 uses a 3-wire serial interface that is compatible with serial peripheral interface (SPI), QSPI™, MICROWIRE™ interface standards, and most digital signal processing (DSP) and the ADG715 is available in a 24-lead TSSOP. interface standards. The output of the shift register DOUT
PRODUCT HIGHLIGHTS
enables a number of these devices to be daisy-chained. 1. 2- or 3-wire serial interface. The ADG715 uses a 2-wire serial interface that is compatible 2. Single-/dual-supply operation. with the I2C interface standard. The ADG715 has four hardwired The ADG714 and ADG715 are fully specified and addresses, selectable from two external address pins (A0 and A1). guaranteed with 3 V, 5 V, and ±2.5 V supply rails. The pins allow the two LSBs of the 7-bit slave address to be set 3. Low on resistance, typically 2.5 Ω. by the user. A maximum of four of these devices may be 4. Low leakage. connected to the bus. 5. Power-on reset. On power-up of these devices, all switches are in the off 6. A 24-lead TSSOP for both the ADG714 and the ADG715. condition, and the internal registers contain all zeros. A 24-lead LFCSP for the ADG714. A low power consumption and operating supply range of 2.7 V to 5.5 V make these devices ideal for many applications. These devices can also be supplied from a dual ±2.5 V supply. The ADG714 is available in a 24-lead TSSOP and a 24-lead LFCSP,
Rev. E Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2000–2018 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
Document Outline Features Applications General Description Functional Block Diagrams Product Highlights Revision History Specifications 5 V Single Supply 3 V Single Supply ±2.5 V Dual Supply Timing Characteristics ADG714 ADG715 Timing Diagrams Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Terminology Theory of Operation Power-On Reset Serial Interface 3-Wire Serial Interface 2-Wire Serial Interface Input Shift Register Write Operation Read Operation Applications Information Multiple Devices on One Bus Daisy-Chaining Multiple ADG714 Devices Power Supply Sequencing Decoding Multiple ADG714 Devices Using the ADG739 Outline Dimensions Ordering Guide
001
SCLK DIN SYNC RESET APPLICATIONS
00043- Figure 1. ADG714 Functional Block Diagram
Data acquisition systems Communication systems ADG715 Relay replacement S1 D1 Audio and video switching S2 D2 S3 D3 GENERAL DESCRIPTION S4 D4
The ADG714/ADG715 are complementary metal-oxide
S5 D5 S6 D6
semiconductor (CMOS), octal single-pole, single-throw (SPST)
S7 D7
switches, controlled via either a 2- or 3-wire serial interface. On
S8 D8
resistance is closely matched between the switches and is flat
INTERFACE
over the full signal range. Each switch conducts equally well in
LOGIC
both directions, and the input signal range extends to the
RESET
002 supplies. Data is written to these devices in the form of 8 bits,
SDA SCL A0 A1
00043- each bit corresponding to one channel. Figure 2. ADG715 Functional Block Diagram The ADG714 uses a 3-wire serial interface that is compatible with serial peripheral interface (SPI), QSPI™, MICROWIRE™ interface standards, and most digital signal processing (DSP) and the ADG715 is available in a 24-lead TSSOP. interface standards. The output of the shift register DOUT
PRODUCT HIGHLIGHTS
enables a number of these devices to be daisy-chained. 1. 2- or 3-wire serial interface. The ADG715 uses a 2-wire serial interface that is compatible 2. Single-/dual-supply operation. with the I2C interface standard. The ADG715 has four hardwired The ADG714 and ADG715 are fully specified and addresses, selectable from two external address pins (A0 and A1). guaranteed with 3 V, 5 V, and ±2.5 V supply rails. The pins allow the two LSBs of the 7-bit slave address to be set 3. Low on resistance, typically 2.5 Ω. by the user. A maximum of four of these devices may be 4. Low leakage. connected to the bus. 5. Power-on reset. On power-up of these devices, all switches are in the off 6. A 24-lead TSSOP for both the ADG714 and the ADG715. condition, and the internal registers contain all zeros. A 24-lead LFCSP for the ADG714. A low power consumption and operating supply range of 2.7 V to 5.5 V make these devices ideal for many applications. These devices can also be supplied from a dual ±2.5 V supply. The ADG714 is available in a 24-lead TSSOP and a 24-lead LFCSP,
Rev. E Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2000–2018 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
Document Outline Features Applications General Description Functional Block Diagrams Product Highlights Revision History Specifications 5 V Single Supply 3 V Single Supply ±2.5 V Dual Supply Timing Characteristics ADG714 ADG715 Timing Diagrams Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Terminology Theory of Operation Power-On Reset Serial Interface 3-Wire Serial Interface 2-Wire Serial Interface Input Shift Register Write Operation Read Operation Applications Information Multiple Devices on One Bus Daisy-Chaining Multiple ADG714 Devices Power Supply Sequencing Decoding Multiple ADG714 Devices Using the ADG739 Outline Dimensions Ordering Guide