Datasheet BlueNRG-LPS (STMicroelectronics) - 10

BlueNRG-LPS Operating modes
• The main LDO (MLDO): – it provides 1.2 V from a 1.4-3.3 V input voltage – it supplies both VDD12i and VDD12o when the device is active – it is disabled during the low power mode (DEEPSTOP) • Low power LDO (LPREG): – it stays enabled during both active and low power phases – it provides 1.0 V voltage – it is not connected to the digital domain when the device is active – it is connected to the VDD12o domain during low power mode (DEEPSTOP) • A dedicated LDO (RFLDO) to provide a 1.2 V to the analog RF block An embedded SMPS step-down converter is available (inserted between the external power and the LDOs).
1.6.4 Power supply supervisor
The BlueNRG-LPS device embeds several power voltage monitoring: • Power-on-reset (POR): during the power-on, the device remains in reset mode if VDDIO is below a VPOR threshold (typically 1.65 V) • Power-down-reset (PDR): during power-down, the PDR puts the device under reset when the supply voltage (VDD) drops below the VPDR threshold (around 20 mV below VPOR). The PDR feature is always enabled • Power voltage detector (PVD): can be used to monitor the VDDIO (against a programmed threshold) or an external analog input signal. When the feature is enabled and the PVD measures a voltage below the comparator, an interrupt is generated (if unmasked)
1.7 Operating modes
Several operating modes are defined for the BlueNRG-LPS: • RUN mode • DEEPSTOP mode • SHUTDOWN mode
Table 2. Relationship between the low power modes and functional blocks Mode SHUTDOWN DEEPSTOP IDLE RUN
CPU OFF OFF OFF ON Flash OFF OFF ON ON RAM OFF ON/OFF granularity 12 kB ON/OFF ON/OFF Radio OFF OFF ON/OFF ON/OFF Supply system OFF OFF ON ( DC-DC ON/OFF) ON ( DC-DC ON/OFF) Register retention OFF ON ON ON HS clock OFF OFF ON ON LS clock OFF ON/OFF ON ON Peripherals OFF OFF ON/OFF ON/OFF Wake-on RTC OFF ON/OFF ON/OFF NA Wake on LPUART OFF ON/OFF ON/OFF NA Wake on IWDG OFF ON/OFF ON/OFF NA Wake-on GPIOs OFF ON/OFF ON/OFF NA Wake-on reset pin ON ON ON NA GPIOs configuration retention PWRC pull-up/pull-down only ON ON ON
DS13819
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Rev 2 page 10/63
Document Outline Features Applications Description 1 Functional overview 1.1 System architecture 1.2 Arm® Cortex®-M0+ core with MPU 1.3 Memories 1.3.1 Embedded Flash memory 1.3.2 Embedded SRAM 1.3.3 Embedded ROM 1.3.4 Embedded OTP 1.3.5 Memory protection unit (MPU) 1.4 Security and safety 1.5 RF subsystem 1.5.1 RF front-end block diagram 1.6 Power supply management 1.6.1 SMPS step-down regulator 1.6.2 Power supply schemes 1.6.3 Linear voltage regulators 1.6.4 Power supply supervisor 1.7 Operating modes 1.7.1 RUN mode 1.7.2 DEEPSTOP mode 1.7.3 SHUTDOWN mode 1.8 Reset management 1.9 Clock management 1.10 Boot mode 1.11 Embedded UART bootloader 1.12 General purpose inputs/outputs (GPIO) 1.13 Direct memory access (DMA) 1.14 Nested vectored interrupt controller (NVIC) 1.15 Analog digital converter (ADC) 1.15.1 Temperature sensor 1.16 True random number generator (RNG) 1.17 Timers and watchdog 1.17.1 General-purpose timers (TIM2, TIM16, TIM17) 1.17.2 Independent watchdog (IWDG) 1.17.3 SysTick timer 1.18 Real-time clock (RTC) 1.19 Inter-integrated circuit interface (I2C) 1.20 Universal synchronous/asynchronous receiver transmitter (USART) 1.21 LPUART 1.22 Serial peripheral interface (SPI) 1.23 Inter-IC sound (I2S) 1.24 Serial wire debug port 1.25 TX and RX event alert 1.26 Direction finding 2 Pinouts and pin description 3 Memory mapping 4 Application circuits 5 Electrical characteristics 5.1 Parameter conditions 5.1.1 Minimum and maximum values 5.1.2 Typical values 5.1.3 Typical curves 5.1.4 Loading capacitor 5.1.5 Pin input voltage 5.2 Absolute maximum ratings 5.3 Operating conditions 5.3.1 Summary of main performance 5.3.2 General operating conditions 5.3.3 RF general characteristics 5.3.4 RF transmitter characteristics 5.3.5 RF receiver characteristics 5.3.6 Embedded reset and power control block characteristics 5.3.7 Supply current characteristics 5.3.8 Wake-up time from low power modes 5.3.9 High speed crystal requirements 5.3.10 Low speed crystal requirements 5.3.11 High speed ring oscillator characteristics 5.3.12 Low speed ring oscillator characteristics 5.3.13 PLL characteristics 5.3.14 Flash memory characteristics 5.3.15 Electrostatic discharge (ESD) 5.3.16 I/O port characteristics 5.3.17 RSTN pin characteristics 5.3.18 ADC characteristics 5.3.19 Temperature sensor characteristics 5.3.20 Timer characteristics 5.3.21 I2C interface characteristics 5.3.22 SPI characteristics 6 Package information 6.1 QFN32 (5x5x0.9, pitch 0.5 mm) package information 6.2 WLCSP36 package information 6.3 Thermal characteristics 7 Ordering information Revision history