Datasheet BlueNRG-LPS (STMicroelectronics)
| 制造商 | STMicroelectronics |
| 描述 | Programmable Bluetooth Low Energy Wireless SoC |
| 页数 / 页 | 63 / 1 — BlueNRG-LPS. Features. Product status link. Product summary. DS13819. Rev … |
| 文件格式/大小 | PDF / 8.2 Mb |
| 文件语言 | 英语 |
BlueNRG-LPS. Features. Product status link. Product summary. DS13819. Rev 2. April 2022
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BlueNRG-LPS
Datasheet Programmable Bluetooth® Low Energy wireless SoC
Features
• Bluetooth Low Energy system-on-chip supporting Bluetooth 5.3 specifications – 2 Mbps data rate – Long range (Coded PHY) – Advertising extensions – Channel selection algorithm #2 – GATT caching – Direction finding (AoA/AoD) – LE Ping procedure – Periodic advertising and periodic advertising sync transfer – LE L2CAP connection-oriented channel
Product status link
– LE power control and path loss monitoring BlueNRG-LPS • Radio – RX sensitivity level: -97 dBm @ 1 Mbps, -104 dBm @ 125 kbps (long range)
Product summary
– Programmable output power up to +8 dBm (at antenna connector) Order code BlueNRG-332xy – Data rate supported: 2 Mbps, 1 Mbps, 500 kbps and 125 kbps – 128 physical connections – Integrated balun – Support for external PA and LNA – BlueNRG core coprocessor (DMA based) for Bluetooth Low Energy timing critical operation – 2.4 GHz proprietary radio driver – Suitable for systems requiring compliance with the following radio frequency regulations: ETSI EN 300 328, EN 300 440, FCC CFR47 part 15, ARIB STD-T66 • Ultra-low power radio performance – 8 nA in SHUTDOWN mode (1.8 V) – 0.8 uA in DEEPSTOP mode (with external LSE and BLE wake-up sources, 1.8 V) – 1.0 uA in DEEPSTOP mode (with internal LSI and BLE wake-up sources, 1.8 V) – 4.3 mA peak current in TX (@ 0 dBm, 3.3 V) – 3.4 mA peak current in RX (@ sensitivity level, 3.3V) • High performance and ultra-low power Arm® Cortex®-M0+ 32-bit, running up to 64 MHz • Dynamic current consumption: 14 µA/MHz • Operating supply voltage: from 1.7 to 3.6 V • -40 ºC to 105 ºC temperature range • Supply and reset management – High efficiency embedded SMPS step-down converter with intelligent bypass mode – Ultra-low power power-on-reset (POR) and power-down-reset (PDR) – Programmable voltage detector (PVD)
DS13819
-
Rev 2
-
April 2022
www.st.com For further information contact your local STMicroelectronics sales office. Document Outline Features Applications Description 1 Functional overview 1.1 System architecture 1.2 Arm® Cortex®-M0+ core with MPU 1.3 Memories 1.3.1 Embedded Flash memory 1.3.2 Embedded SRAM 1.3.3 Embedded ROM 1.3.4 Embedded OTP 1.3.5 Memory protection unit (MPU) 1.4 Security and safety 1.5 RF subsystem 1.5.1 RF front-end block diagram 1.6 Power supply management 1.6.1 SMPS step-down regulator 1.6.2 Power supply schemes 1.6.3 Linear voltage regulators 1.6.4 Power supply supervisor 1.7 Operating modes 1.7.1 RUN mode 1.7.2 DEEPSTOP mode 1.7.3 SHUTDOWN mode 1.8 Reset management 1.9 Clock management 1.10 Boot mode 1.11 Embedded UART bootloader 1.12 General purpose inputs/outputs (GPIO) 1.13 Direct memory access (DMA) 1.14 Nested vectored interrupt controller (NVIC) 1.15 Analog digital converter (ADC) 1.15.1 Temperature sensor 1.16 True random number generator (RNG) 1.17 Timers and watchdog 1.17.1 General-purpose timers (TIM2, TIM16, TIM17) 1.17.2 Independent watchdog (IWDG) 1.17.3 SysTick timer 1.18 Real-time clock (RTC) 1.19 Inter-integrated circuit interface (I2C) 1.20 Universal synchronous/asynchronous receiver transmitter (USART) 1.21 LPUART 1.22 Serial peripheral interface (SPI) 1.23 Inter-IC sound (I2S) 1.24 Serial wire debug port 1.25 TX and RX event alert 1.26 Direction finding 2 Pinouts and pin description 3 Memory mapping 4 Application circuits 5 Electrical characteristics 5.1 Parameter conditions 5.1.1 Minimum and maximum values 5.1.2 Typical values 5.1.3 Typical curves 5.1.4 Loading capacitor 5.1.5 Pin input voltage 5.2 Absolute maximum ratings 5.3 Operating conditions 5.3.1 Summary of main performance 5.3.2 General operating conditions 5.3.3 RF general characteristics 5.3.4 RF transmitter characteristics 5.3.5 RF receiver characteristics 5.3.6 Embedded reset and power control block characteristics 5.3.7 Supply current characteristics 5.3.8 Wake-up time from low power modes 5.3.9 High speed crystal requirements 5.3.10 Low speed crystal requirements 5.3.11 High speed ring oscillator characteristics 5.3.12 Low speed ring oscillator characteristics 5.3.13 PLL characteristics 5.3.14 Flash memory characteristics 5.3.15 Electrostatic discharge (ESD) 5.3.16 I/O port characteristics 5.3.17 RSTN pin characteristics 5.3.18 ADC characteristics 5.3.19 Temperature sensor characteristics 5.3.20 Timer characteristics 5.3.21 I2C interface characteristics 5.3.22 SPI characteristics 6 Package information 6.1 QFN32 (5x5x0.9, pitch 0.5 mm) package information 6.2 WLCSP36 package information 6.3 Thermal characteristics 7 Ordering information Revision history
Datasheet Programmable Bluetooth® Low Energy wireless SoC
Features
• Bluetooth Low Energy system-on-chip supporting Bluetooth 5.3 specifications – 2 Mbps data rate – Long range (Coded PHY) – Advertising extensions – Channel selection algorithm #2 – GATT caching – Direction finding (AoA/AoD) – LE Ping procedure – Periodic advertising and periodic advertising sync transfer – LE L2CAP connection-oriented channel
Product status link
– LE power control and path loss monitoring BlueNRG-LPS • Radio – RX sensitivity level: -97 dBm @ 1 Mbps, -104 dBm @ 125 kbps (long range)
Product summary
– Programmable output power up to +8 dBm (at antenna connector) Order code BlueNRG-332xy – Data rate supported: 2 Mbps, 1 Mbps, 500 kbps and 125 kbps – 128 physical connections – Integrated balun – Support for external PA and LNA – BlueNRG core coprocessor (DMA based) for Bluetooth Low Energy timing critical operation – 2.4 GHz proprietary radio driver – Suitable for systems requiring compliance with the following radio frequency regulations: ETSI EN 300 328, EN 300 440, FCC CFR47 part 15, ARIB STD-T66 • Ultra-low power radio performance – 8 nA in SHUTDOWN mode (1.8 V) – 0.8 uA in DEEPSTOP mode (with external LSE and BLE wake-up sources, 1.8 V) – 1.0 uA in DEEPSTOP mode (with internal LSI and BLE wake-up sources, 1.8 V) – 4.3 mA peak current in TX (@ 0 dBm, 3.3 V) – 3.4 mA peak current in RX (@ sensitivity level, 3.3V) • High performance and ultra-low power Arm® Cortex®-M0+ 32-bit, running up to 64 MHz • Dynamic current consumption: 14 µA/MHz • Operating supply voltage: from 1.7 to 3.6 V • -40 ºC to 105 ºC temperature range • Supply and reset management – High efficiency embedded SMPS step-down converter with intelligent bypass mode – Ultra-low power power-on-reset (POR) and power-down-reset (PDR) – Programmable voltage detector (PVD)
DS13819
-
Rev 2
-
April 2022
www.st.com For further information contact your local STMicroelectronics sales office. Document Outline Features Applications Description 1 Functional overview 1.1 System architecture 1.2 Arm® Cortex®-M0+ core with MPU 1.3 Memories 1.3.1 Embedded Flash memory 1.3.2 Embedded SRAM 1.3.3 Embedded ROM 1.3.4 Embedded OTP 1.3.5 Memory protection unit (MPU) 1.4 Security and safety 1.5 RF subsystem 1.5.1 RF front-end block diagram 1.6 Power supply management 1.6.1 SMPS step-down regulator 1.6.2 Power supply schemes 1.6.3 Linear voltage regulators 1.6.4 Power supply supervisor 1.7 Operating modes 1.7.1 RUN mode 1.7.2 DEEPSTOP mode 1.7.3 SHUTDOWN mode 1.8 Reset management 1.9 Clock management 1.10 Boot mode 1.11 Embedded UART bootloader 1.12 General purpose inputs/outputs (GPIO) 1.13 Direct memory access (DMA) 1.14 Nested vectored interrupt controller (NVIC) 1.15 Analog digital converter (ADC) 1.15.1 Temperature sensor 1.16 True random number generator (RNG) 1.17 Timers and watchdog 1.17.1 General-purpose timers (TIM2, TIM16, TIM17) 1.17.2 Independent watchdog (IWDG) 1.17.3 SysTick timer 1.18 Real-time clock (RTC) 1.19 Inter-integrated circuit interface (I2C) 1.20 Universal synchronous/asynchronous receiver transmitter (USART) 1.21 LPUART 1.22 Serial peripheral interface (SPI) 1.23 Inter-IC sound (I2S) 1.24 Serial wire debug port 1.25 TX and RX event alert 1.26 Direction finding 2 Pinouts and pin description 3 Memory mapping 4 Application circuits 5 Electrical characteristics 5.1 Parameter conditions 5.1.1 Minimum and maximum values 5.1.2 Typical values 5.1.3 Typical curves 5.1.4 Loading capacitor 5.1.5 Pin input voltage 5.2 Absolute maximum ratings 5.3 Operating conditions 5.3.1 Summary of main performance 5.3.2 General operating conditions 5.3.3 RF general characteristics 5.3.4 RF transmitter characteristics 5.3.5 RF receiver characteristics 5.3.6 Embedded reset and power control block characteristics 5.3.7 Supply current characteristics 5.3.8 Wake-up time from low power modes 5.3.9 High speed crystal requirements 5.3.10 Low speed crystal requirements 5.3.11 High speed ring oscillator characteristics 5.3.12 Low speed ring oscillator characteristics 5.3.13 PLL characteristics 5.3.14 Flash memory characteristics 5.3.15 Electrostatic discharge (ESD) 5.3.16 I/O port characteristics 5.3.17 RSTN pin characteristics 5.3.18 ADC characteristics 5.3.19 Temperature sensor characteristics 5.3.20 Timer characteristics 5.3.21 I2C interface characteristics 5.3.22 SPI characteristics 6 Package information 6.1 QFN32 (5x5x0.9, pitch 0.5 mm) package information 6.2 WLCSP36 package information 6.3 Thermal characteristics 7 Ordering information Revision history