Datasheet L6562 (STMicroelectronics) - 3
| 制造商 | STMicroelectronics |
| 描述 | Transition-Mode PFC Controller |
| 页数 / 页 | 16 / 3 — L6562. Table 4. Pin Description. Pin. Function. Table 5. Electrical … |
| 文件语言 | 英语 |
L6562. Table 4. Pin Description. Pin. Function. Table 5. Electrical Characteristics. Symbol. Parameter. Test Condition. Min. Typ. Max. Unit
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L6562 Table 4. Pin Description N° Pin Function
1 INV Inverting input of the error amplifier. The information on the output voltage of the PFC pre- regulator is fed into the pin through a resistor divider. 2 COMP Output of the error amplifier. A compensation network is placed between this pin and INV (pin #1) to achieve stability of the voltage control loop and ensure high power factor and low THD. 3 MULT Main input to the multiplier. This pin is connected to the rectified mains voltage via a resistor divider and provides the sinusoidal reference to the current loop. 4 CS Input to the PWM comparator. The current flowing in the MOSFET is sensed through a resistor, the resulting voltage is applied to this pin and compared with an internal sinusoidal-shaped reference, generated by the multiplier, to determine MOSFET’s turn-off. 5 ZCD Boost inductor’s demagnetization sensing input for transition-mode operation. A negative-going edge triggers MOSFET’s turn-on. 6 GND Ground. Current return for both the signal part of the IC and the gate driver. 7 GD Gate driver output. The totem pole output stage is able to drive power MOSFET’s and IGBT’s with a peak current of 600 mA source and 800 mA sink. The high-level voltage of this pin is clamped at about 12V to avoid excessive gate voltages in case the pin is supplied with a high Vcc. 8 Vcc Supply Voltage of both the signal part of the IC and the gate driver. The supply voltage upper limit is extended to 22V min. to provide more headroom for supply voltage changes.
Table 5. Electrical Characteristics
(Tj = -25 to 125°C, VCC = 12, CO = 1 nF; unless otherwise specified)
Symbol Parameter Test Condition Min. Typ. Max. Unit SUPPLY VOLTAGE
VCC Operating range After turn-on 10.3 22 V VCCon Turn-on threshold (1) 11 12 13 V VCCOff Turn-off threshold (1) 8.7 9.5 10.3 V Hys Hysteresis 2.2 2.8 V VZ Zener Voltage ICC = 20 mA 22 25 28 V
SUPPLY CURRENT
Istart-up Start-up Current Before turn-on, VCC =11V 40 70 µA Iq Quiescent Current After turn-on 2.5 3.75 mA ICC Operating Supply Current @ 70 kHz 3.5 5 mA Iq Quiescent Current During OVP (either static or 2.2 mA dynamic) or VZCD =150 mV
MULTIPLIER INPUT
IMULT Input Bias Current VVFF = 0 to 4 V -1 µA VMULT Linear Operation Range 0 to 3 V Output Max. Slope V V ∆ MULT = 0 to 0.5V 1.65 1.9 V/V C S ------------ VCOMP = Upper clamp V ∆ MULT K Gain (2) VMULT = 1 V, VCOMP = 4 V 0.5 0.6 0.7 1/V
ERROR AMPLIFIER
VINV Voltage Feedback Input Tj = 25 °C 2.465 2.5 2.535 V Threshold 10.3 V < Vcc < 22 V (1) 2.44 2.56 Line Regulation Vcc = 10.3 V to 22V 2 5 mV IINV Input Bias Current VINV = 0 to 3 V -1 µA 3/16 Document Outline Figure 1. Packages Table 1. Order Codes 1 Features 1.1 APPLICATIONS 2 Description Figure 2. Block Diagram Table 2. Absolute Maximum Ratings Figure 3. Pin Connection (Top view) Table 3. Thermal Data Table 4. Pin Description Table 5. Electrical Characteristics (Tj = -25 to 125˚C, VCC = 12, CO = 1 nF; unless otherwise specified) 3 Typical Electrical Characteristics Figure 4. Supply current vs. Supply voltage Figure 5. Start-up & UVLO vs. Tj Figure 6. IC consumption vs. Tj Figure 7. Vcc Zener voltage vs. Tj Figure 8. Feedback reference vs. Tj Figure 9. OVP current vs. Tj Figure 10. E/A output clamp levels vs. Tj Figure 11. Delay-to-output vs. Tj Figure 12. Multiplier characteristic Figure 13. Multiplier gain vs. Tj Figure 14. Vcs clamp vs. Tj Figure 15. Start-up timer vs. Tj Figure 16. ZCD clamp levels vs. Tj Figure 17. ZCD source capability vs. Tj Figure 18. Gate-drive output low saturation Figure 19. Gate-drive output high saturation Figure 20. Gate-drive clamp vs. Tj Figure 21. UVLO saturation vs. Tj 4 Application Information 4.1 Overvoltage protection 4.2 THD optimizer circuit Figure 22. THD optimization: standard TM PFC controller (left side) and L6562 (right side) Figure 23. Typical application circuit (250W, Wide-range mains) Figure 24. Demo board (EVAL6562-80W, Wide-range mains): Electrical schematic Figure 25. EVAL6562-80W: PCB and component layout (Top view, real size: 57 x 108 mm) Table 6. EVAL6562N: Evaluation results at full load Table 7. EVAL6562N: Evaluation results at half load Table 8. EVAL6562N: No-load measurements Figure 26. Line filter (not tested for EMI compliance) used for EVAL6562N evaluation 5 Package Information Figure 27. DIP-8 Mechanical Data & Package Dimensions Figure 28. SO-8 Mechanical Data & Package Dimensions 6 Revision History Table 9. Revision History
1 INV Inverting input of the error amplifier. The information on the output voltage of the PFC pre- regulator is fed into the pin through a resistor divider. 2 COMP Output of the error amplifier. A compensation network is placed between this pin and INV (pin #1) to achieve stability of the voltage control loop and ensure high power factor and low THD. 3 MULT Main input to the multiplier. This pin is connected to the rectified mains voltage via a resistor divider and provides the sinusoidal reference to the current loop. 4 CS Input to the PWM comparator. The current flowing in the MOSFET is sensed through a resistor, the resulting voltage is applied to this pin and compared with an internal sinusoidal-shaped reference, generated by the multiplier, to determine MOSFET’s turn-off. 5 ZCD Boost inductor’s demagnetization sensing input for transition-mode operation. A negative-going edge triggers MOSFET’s turn-on. 6 GND Ground. Current return for both the signal part of the IC and the gate driver. 7 GD Gate driver output. The totem pole output stage is able to drive power MOSFET’s and IGBT’s with a peak current of 600 mA source and 800 mA sink. The high-level voltage of this pin is clamped at about 12V to avoid excessive gate voltages in case the pin is supplied with a high Vcc. 8 Vcc Supply Voltage of both the signal part of the IC and the gate driver. The supply voltage upper limit is extended to 22V min. to provide more headroom for supply voltage changes.
Table 5. Electrical Characteristics
(Tj = -25 to 125°C, VCC = 12, CO = 1 nF; unless otherwise specified)
Symbol Parameter Test Condition Min. Typ. Max. Unit SUPPLY VOLTAGE
VCC Operating range After turn-on 10.3 22 V VCCon Turn-on threshold (1) 11 12 13 V VCCOff Turn-off threshold (1) 8.7 9.5 10.3 V Hys Hysteresis 2.2 2.8 V VZ Zener Voltage ICC = 20 mA 22 25 28 V
SUPPLY CURRENT
Istart-up Start-up Current Before turn-on, VCC =11V 40 70 µA Iq Quiescent Current After turn-on 2.5 3.75 mA ICC Operating Supply Current @ 70 kHz 3.5 5 mA Iq Quiescent Current During OVP (either static or 2.2 mA dynamic) or VZCD =150 mV
MULTIPLIER INPUT
IMULT Input Bias Current VVFF = 0 to 4 V -1 µA VMULT Linear Operation Range 0 to 3 V Output Max. Slope V V ∆ MULT = 0 to 0.5V 1.65 1.9 V/V C S ------------ VCOMP = Upper clamp V ∆ MULT K Gain (2) VMULT = 1 V, VCOMP = 4 V 0.5 0.6 0.7 1/V
ERROR AMPLIFIER
VINV Voltage Feedback Input Tj = 25 °C 2.465 2.5 2.535 V Threshold 10.3 V < Vcc < 22 V (1) 2.44 2.56 Line Regulation Vcc = 10.3 V to 22V 2 5 mV IINV Input Bias Current VINV = 0 to 3 V -1 µA 3/16 Document Outline Figure 1. Packages Table 1. Order Codes 1 Features 1.1 APPLICATIONS 2 Description Figure 2. Block Diagram Table 2. Absolute Maximum Ratings Figure 3. Pin Connection (Top view) Table 3. Thermal Data Table 4. Pin Description Table 5. Electrical Characteristics (Tj = -25 to 125˚C, VCC = 12, CO = 1 nF; unless otherwise specified) 3 Typical Electrical Characteristics Figure 4. Supply current vs. Supply voltage Figure 5. Start-up & UVLO vs. Tj Figure 6. IC consumption vs. Tj Figure 7. Vcc Zener voltage vs. Tj Figure 8. Feedback reference vs. Tj Figure 9. OVP current vs. Tj Figure 10. E/A output clamp levels vs. Tj Figure 11. Delay-to-output vs. Tj Figure 12. Multiplier characteristic Figure 13. Multiplier gain vs. Tj Figure 14. Vcs clamp vs. Tj Figure 15. Start-up timer vs. Tj Figure 16. ZCD clamp levels vs. Tj Figure 17. ZCD source capability vs. Tj Figure 18. Gate-drive output low saturation Figure 19. Gate-drive output high saturation Figure 20. Gate-drive clamp vs. Tj Figure 21. UVLO saturation vs. Tj 4 Application Information 4.1 Overvoltage protection 4.2 THD optimizer circuit Figure 22. THD optimization: standard TM PFC controller (left side) and L6562 (right side) Figure 23. Typical application circuit (250W, Wide-range mains) Figure 24. Demo board (EVAL6562-80W, Wide-range mains): Electrical schematic Figure 25. EVAL6562-80W: PCB and component layout (Top view, real size: 57 x 108 mm) Table 6. EVAL6562N: Evaluation results at full load Table 7. EVAL6562N: Evaluation results at half load Table 8. EVAL6562N: No-load measurements Figure 26. Line filter (not tested for EMI compliance) used for EVAL6562N evaluation 5 Package Information Figure 27. DIP-8 Mechanical Data & Package Dimensions Figure 28. SO-8 Mechanical Data & Package Dimensions 6 Revision History Table 9. Revision History