Datasheet L6562 (STMicroelectronics) - 10

L6562
the output of the multiplier in the proximity of the line voltage zero-crossings. This offset is reduced as the instantaneous line voltage increases, so that it becomes negligible as the line voltage moves toward the top of the sinusoid. To maximally benefit from the THD optimizer circuit, the high-frequency filter capacitor after the bridge rec- tifier should be minimized, compatibly with EMI filtering needs. A large capacitance, in fact, introduces a conduction dead-angle of the AC input current in itself - even with an ideal energy transfer by the PFC pre- regulator - thus making the action of the optimizer circuit little effective.
Figure 23. Typical application circuit (250W, Wide-range mains)
D3 1N5406 T R4 R5 D8 D1 NTC Vo=400V 180 kΩ C5 12 nF 180 kΩ 1N4150 R14 STTH5L06 2.5 Ω R11 Po=250W 750 kΩ 100 Ω R50 10 kΩ R1 D2 R12 1.5 MΩ 1N5248B R6 750 kΩ C3 2.2 µF 68 kΩ BRIDGE C1 C23 STBR606 1 µF FUSE + 680 nF 400V 5A/250V R2 8 5 2 1 R7 1.5 MΩ 10 Ω C6 MOS 3 - L6562 7 100 µF STP12NM50 Vac 7 °C/W heat sink 450V (85V to 265V) 6 4 C2 10nF C29 R3 22 µF C4 R9 R10 R13 22 kΩ 100 nF 25V 0.33Ω 0.33Ω 9.53 kΩ 1W 1W - Boost Inductor Spec: EB0057-C (
COILCRAFT
)
Figure 24. Demo board (EVAL6562-80W, Wide-range mains): Electrical schematic
T R4 R5 D8 D1 NTC Vo=400V 180 kΩ C5 12 nF 180 kΩ 1N4150 R14 STTH1L06 2.5 Ω R11 Po=80W 750 kΩ 100 Ω R50 12 kΩ R1 D2 R12 750 kΩ 1N5248B R6 750 kΩ C3 680 nF 68 kΩ BRIDGE C1 C23 DF06M 0.47 µF 330 nF FUSE + 400V 4A/250V R2 8 5 2 1 R7 750 kΩ 33 Ω MOS C6 3 - L6562 7 STP8NM50 47 µF Vac 450V (85V to 265V) 6 4 C2 10nF C29 R3 22 µF C4 R9 R10 R13 10 kΩ 100 nF 25V 0.82Ω 0.82Ω 9.53 kΩ 0.6 W 0.6 W - Boost Inductor Spec (ITACOIL E2543/E) E25x13x7 core, 3C85 ferrite 1.5 mm gap for 0.7 mH primary inductance Primary: 105 turns 20x0.1 mm Secondary: 11 turns 0.1 mm 10/16 Document Outline Figure 1. Packages Table 1. Order Codes 1 Features 1.1 APPLICATIONS 2 Description Figure 2. Block Diagram Table 2. Absolute Maximum Ratings Figure 3. Pin Connection (Top view) Table 3. Thermal Data Table 4. Pin Description Table 5. Electrical Characteristics (Tj = -25 to 125˚C, VCC = 12, CO = 1 nF; unless otherwise specified) 3 Typical Electrical Characteristics Figure 4. Supply current vs. Supply voltage Figure 5. Start-up & UVLO vs. Tj Figure 6. IC consumption vs. Tj Figure 7. Vcc Zener voltage vs. Tj Figure 8. Feedback reference vs. Tj Figure 9. OVP current vs. Tj Figure 10. E/A output clamp levels vs. Tj Figure 11. Delay-to-output vs. Tj Figure 12. Multiplier characteristic Figure 13. Multiplier gain vs. Tj Figure 14. Vcs clamp vs. Tj Figure 15. Start-up timer vs. Tj Figure 16. ZCD clamp levels vs. Tj Figure 17. ZCD source capability vs. Tj Figure 18. Gate-drive output low saturation Figure 19. Gate-drive output high saturation Figure 20. Gate-drive clamp vs. Tj Figure 21. UVLO saturation vs. Tj 4 Application Information 4.1 Overvoltage protection 4.2 THD optimizer circuit Figure 22. THD optimization: standard TM PFC controller (left side) and L6562 (right side) Figure 23. Typical application circuit (250W, Wide-range mains) Figure 24. Demo board (EVAL6562-80W, Wide-range mains): Electrical schematic Figure 25. EVAL6562-80W: PCB and component layout (Top view, real size: 57 x 108 mm) Table 6. EVAL6562N: Evaluation results at full load Table 7. EVAL6562N: Evaluation results at half load Table 8. EVAL6562N: No-load measurements Figure 26. Line filter (not tested for EMI compliance) used for EVAL6562N evaluation 5 Package Information Figure 27. DIP-8 Mechanical Data & Package Dimensions Figure 28. SO-8 Mechanical Data & Package Dimensions 6 Revision History Table 9. Revision History