Datasheet L6562 (STMicroelectronics) - 7
| 制造商 | STMicroelectronics |
| 描述 | Transition-Mode PFC Controller |
| 页数 / 页 | 16 / 7 — L6562. Figure 14. Vcs clamp vs. T. Figure 17. ZCD source capability vs. … |
| 文件语言 | 英语 |
L6562. Figure 14. Vcs clamp vs. T. Figure 17. ZCD source capability vs. T. Figure 15. Start-up timer vs. T
该数据表的模型线
文件文字版本
L6562 Figure 14. Vcs clamp vs. T
j
Figure 17. ZCD source capability vs. T
j VCSx IZCDsrc 2 0 (V) (mA) Vcc = 12 V VZCD= lower clamp 1.8 -2 1.6 -4 1.4 Vcc = 12 V -6 1.2 VCOMP = Upper clamp 1 -8 -50 0 50 100 150 -50 0 50 100 150 Tj (°C) Tj (°C)
Figure 15. Start-up timer vs. T
j
Figure 18. Gate-drive output low saturation
Tstart 150 Vpin7[V] (µs) Vcc = 12 V 4 Tj = 25 °C 140 Vcc = 11 V SINK 3 130 2 120 1 110 100 00 200 400 600 800 1,000 -50 0 50 100 150 I Tj (°C) GD[mA]
Figure 16. ZCD clamp levels vs. T
j
Figure 19. Gate-drive output high saturation
VZCD Vpin7[V] 7 (V) -1.5 Upper clamp 6 Tj = 25 °C Vcc - 2 -2 Vcc = 11 V .0 SOURCE 5 Vcc = 12 V IZCD = ±2.5 mA -2.5 Vcc - 2.5 4 -3 Vcc - 3.0 3 V -3.5 cc - 3.5 2 Vcc - 4 -4 .0 1 Lower clamp -4.5 0 0 100 200 300 400 500 600 700 -50 0 50 100 150 IGD[mA] Tj (°C) 7/16 Document Outline Figure 1. Packages Table 1. Order Codes 1 Features 1.1 APPLICATIONS 2 Description Figure 2. Block Diagram Table 2. Absolute Maximum Ratings Figure 3. Pin Connection (Top view) Table 3. Thermal Data Table 4. Pin Description Table 5. Electrical Characteristics (Tj = -25 to 125˚C, VCC = 12, CO = 1 nF; unless otherwise specified) 3 Typical Electrical Characteristics Figure 4. Supply current vs. Supply voltage Figure 5. Start-up & UVLO vs. Tj Figure 6. IC consumption vs. Tj Figure 7. Vcc Zener voltage vs. Tj Figure 8. Feedback reference vs. Tj Figure 9. OVP current vs. Tj Figure 10. E/A output clamp levels vs. Tj Figure 11. Delay-to-output vs. Tj Figure 12. Multiplier characteristic Figure 13. Multiplier gain vs. Tj Figure 14. Vcs clamp vs. Tj Figure 15. Start-up timer vs. Tj Figure 16. ZCD clamp levels vs. Tj Figure 17. ZCD source capability vs. Tj Figure 18. Gate-drive output low saturation Figure 19. Gate-drive output high saturation Figure 20. Gate-drive clamp vs. Tj Figure 21. UVLO saturation vs. Tj 4 Application Information 4.1 Overvoltage protection 4.2 THD optimizer circuit Figure 22. THD optimization: standard TM PFC controller (left side) and L6562 (right side) Figure 23. Typical application circuit (250W, Wide-range mains) Figure 24. Demo board (EVAL6562-80W, Wide-range mains): Electrical schematic Figure 25. EVAL6562-80W: PCB and component layout (Top view, real size: 57 x 108 mm) Table 6. EVAL6562N: Evaluation results at full load Table 7. EVAL6562N: Evaluation results at half load Table 8. EVAL6562N: No-load measurements Figure 26. Line filter (not tested for EMI compliance) used for EVAL6562N evaluation 5 Package Information Figure 27. DIP-8 Mechanical Data & Package Dimensions Figure 28. SO-8 Mechanical Data & Package Dimensions 6 Revision History Table 9. Revision History
j
Figure 17. ZCD source capability vs. T
j VCSx IZCDsrc 2 0 (V) (mA) Vcc = 12 V VZCD= lower clamp 1.8 -2 1.6 -4 1.4 Vcc = 12 V -6 1.2 VCOMP = Upper clamp 1 -8 -50 0 50 100 150 -50 0 50 100 150 Tj (°C) Tj (°C)
Figure 15. Start-up timer vs. T
j
Figure 18. Gate-drive output low saturation
Tstart 150 Vpin7[V] (µs) Vcc = 12 V 4 Tj = 25 °C 140 Vcc = 11 V SINK 3 130 2 120 1 110 100 00 200 400 600 800 1,000 -50 0 50 100 150 I Tj (°C) GD[mA]
Figure 16. ZCD clamp levels vs. T
j
Figure 19. Gate-drive output high saturation
VZCD Vpin7[V] 7 (V) -1.5 Upper clamp 6 Tj = 25 °C Vcc - 2 -2 Vcc = 11 V .0 SOURCE 5 Vcc = 12 V IZCD = ±2.5 mA -2.5 Vcc - 2.5 4 -3 Vcc - 3.0 3 V -3.5 cc - 3.5 2 Vcc - 4 -4 .0 1 Lower clamp -4.5 0 0 100 200 300 400 500 600 700 -50 0 50 100 150 IGD[mA] Tj (°C) 7/16 Document Outline Figure 1. Packages Table 1. Order Codes 1 Features 1.1 APPLICATIONS 2 Description Figure 2. Block Diagram Table 2. Absolute Maximum Ratings Figure 3. Pin Connection (Top view) Table 3. Thermal Data Table 4. Pin Description Table 5. Electrical Characteristics (Tj = -25 to 125˚C, VCC = 12, CO = 1 nF; unless otherwise specified) 3 Typical Electrical Characteristics Figure 4. Supply current vs. Supply voltage Figure 5. Start-up & UVLO vs. Tj Figure 6. IC consumption vs. Tj Figure 7. Vcc Zener voltage vs. Tj Figure 8. Feedback reference vs. Tj Figure 9. OVP current vs. Tj Figure 10. E/A output clamp levels vs. Tj Figure 11. Delay-to-output vs. Tj Figure 12. Multiplier characteristic Figure 13. Multiplier gain vs. Tj Figure 14. Vcs clamp vs. Tj Figure 15. Start-up timer vs. Tj Figure 16. ZCD clamp levels vs. Tj Figure 17. ZCD source capability vs. Tj Figure 18. Gate-drive output low saturation Figure 19. Gate-drive output high saturation Figure 20. Gate-drive clamp vs. Tj Figure 21. UVLO saturation vs. Tj 4 Application Information 4.1 Overvoltage protection 4.2 THD optimizer circuit Figure 22. THD optimization: standard TM PFC controller (left side) and L6562 (right side) Figure 23. Typical application circuit (250W, Wide-range mains) Figure 24. Demo board (EVAL6562-80W, Wide-range mains): Electrical schematic Figure 25. EVAL6562-80W: PCB and component layout (Top view, real size: 57 x 108 mm) Table 6. EVAL6562N: Evaluation results at full load Table 7. EVAL6562N: Evaluation results at half load Table 8. EVAL6562N: No-load measurements Figure 26. Line filter (not tested for EMI compliance) used for EVAL6562N evaluation 5 Package Information Figure 27. DIP-8 Mechanical Data & Package Dimensions Figure 28. SO-8 Mechanical Data & Package Dimensions 6 Revision History Table 9. Revision History