Datasheet NE570 (ON Semiconductor) - 6

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NE570 CIRCUIT DETAILS−RECTIFIER
respectively. ICs such as this have typical NPN β’s of 200 Figure 8 shows the concept behind the full−wave and PNP β’s of 40. The α’s of 0.995 and 0.975 will produce averaging rectifier. The input current to the summing node errors of 0.5% on negative swings and 2.5% on positive of the op amp, VIN/R1, is supplied by the output of the op swings. The 1.5% average of these errors yields a mere amp. If we can mirror the op amp output current into a 0.13 dB gain error. unipolar current, we will have an ideal rectifier. The output At very low input signal levels the bias current of Q2, current is averaged by R5, CR, which set the averaging time (typically 50 nA), will become significant as it must be constant, and then mirrored with a gain of 2 to become IG, supplied by Q5. Another low level error can be caused by DC the gain control current. coupling into the rectifier. If an offset voltage exists between Figure 9 shows the rectifier circuit in more detail. The op the VIN input pin and the base of Q2, an error current of amp is a one−stage op amp, biased so that only one output VOS/R1 will be generated. A mere 1.0 mV of offset will device is on at a time. The non−inverting input, (the base of cause an input current of 100 nA, which will produce twice Q1), which is shown grounded, is actually tied to the internal the error of the input bias current. For highest accuracy, the 1.8 V VREF. The inverting input is tied to the op amp output, rectifier should be coupled capacitively. At high input levels (the emitters of Q5 and Q6), and the input summing resistor the β of the PNP Q6 will begin to suffer, and there will be an R1. The single diode between the bases of Q5 and Q6 assures increasing error until the circuit saturates. Saturation can be that only one device is on at a time. To detect the output avoided by limiting the current into the rectifier input to current of the op amp, we simply use the collector currents of 250 mA. If necessary, an external resistor may be placed in the output devices Q5 and Q6. Q6 will conduct when the series with R1 to limit the current to this value. Figure 10 input swings positive and Q5 conducts when the input shows the rectifier accuracy versus input level at a frequency swings negative. The collector currents will be in error by the of 1.0 kHz. α of Q5 or Q6 on negative or positive signal swings, V+ V+ Q Q 3 7 I = VIN/R1 Q4 R1 Q − 5 VIN R1 + D1 10 kW Q1 Q2 V R IN 5 R 10 kW 5 I C G 10 kW R Q6 Q8 Q9 I1 I2 CR NOTE: V− V I IN avg G = 2 R1
Figure 8. Rectifier Concept Figure 9. Simplified Rectifier Schematic
+1 0 ERROR GAIN dB −1 −40 −20 0 RECTIFIER INPUT dBm
Figure 10. Rectifier Accuracy http://onsemi.com 6