Datasheet NE570 (ON Semiconductor) - 7

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NE570
At very high frequencies, the response of the rectifier will The op amp maintains the base and collector of Q1 at fall off. The roll−off will be more pronounced at lower input ground potential (VREF) by controlling the base of Q2. The levels due to the increasing amount of gain required to switch input current IIN (= VIN/R2) is thus forced to flow through between Q5 or Q6 conducting. The rectifier frequency Q1 along with the current I1, so IC1 = I1 + IIN. Since I2 has response for input levels of 0 dBm, −20 dBm, and −40 dBm been set at twice the value of I1, the current through Q2 is: is shown in Figure 11. The response at all three levels is flat I2 * (I1 ) IIN) + I1 * IIN + IC2. to well above the audio range. The op amp has thus forced a linear current swing between Q1 and Q2 by providing the proper drive to the base of Q2. This drive signal will be linear for small signals, but very non−linear for large signals, since it is compensating for the INPUT = 0 dBm non−linearity of the differential pair, Q1 and Q2, under large 0 −20 dBm signal conditions. The key to the circuit is that this same predistorted drive 3 −40 dBm signal is applied to the gain control pair, Q3 and Q4. When GAIN ERROR (dB) two differential pairs of transistors have the same signal applied, their collector current ratios will be identical regardless of the magnitude of the currents. This gives us: I I I ) I 10 k 1 MEG C1 + C4 + 1 IN * FREQUENCY (Hz) I I I I C2 C3 1 IN plus the relationships I
Figure 11. Rectifier Frequency Response
G = IC3 + IC4 and IOUT = IC4 − IC3 will yield the multiplier transfer function,
vs. Input Level
I V I I + G I + IN G OUT I IN R I 1 2 1
VARIABLE GAIN CELL
This equation is linear and temperature−insensitive, but it Figure 12 is a diagram of the variable gain cell. This is a assumes ideal transistors. linearized two−quadrant transconductance multiplier. Q1, Q2 and the op amp provide a predistorted drive signal for the 4 gain control pair, Q3 and Q4. The gain is controlled by IG and VOS = 5 mV a current mirror provides the output current. 3 4 mV V+ 2 3 mV
I1
% THD
140
m
A
2 mv 1 − 1 mV + 0.34
R2 20 k
W −6 0 +6 Q V 1 Q2 Q3 Q IN 4 INPUT LEVEL (dBm) IIN
Figure 13.
D
G Cell Distortion vs. Offset Voltage I2 ( = 2 I1 ) IG 280
m
A
If the transistors are not perfectly matched, a parabolic,
NOTE:
V− non−linearity is generated, which results in second IG I V G IN IOUT = I harmonic distortion. Figure 13 gives an indication of the I IN = 1 I R 1 2 magnitude of the distortion caused by a given input level and
Figure 12. Simplified
D
G Cell Schematic
offset voltage. The distortion is linearly proportional to the magnitude of the offset and the input level. Saturation of the gain cell occurs at a +8.0 dBm level. At a nominal operating level of 0 dBm, a 1.0 mV offset will yield 0.34% of second harmonic distortion. Most circuits are somewhat better than
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