Datasheet OPA206, OPA2206, OPA4206 (Texas Instruments) - 3
| 制造商 | Texas Instruments |
| 描述 | Input-overvoltage-protected, low-power, low-noise four-channel op amp with super-beta inputs |
| 页数 / 页 | 48 / 3 — OPA206. , OPA2206. , OPA4206. www.ti.com. 4 Pin Configuration and … |
| 文件格式/大小 | PDF / 3.3 Mb |
| 文件语言 | 英语 |
OPA206. , OPA2206. , OPA4206. www.ti.com. 4 Pin Configuration and Functions. Figure 4-1. OPA206: D Package, 8-Pin SOIC (Top View)
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OPA206 , OPA2206 , OPA4206 www.ti.com
SBOSA11E – MARCH 2020 – REVISED DECEMBER 2023
4 Pin Configuration and Functions
NC 1 8 NC 2 ±IN ± 7 V+ +IN 3 + 6 OUT V 4 ± 5 NC Not to scale
Figure 4-1. OPA206: D Package, 8-Pin SOIC (Top View) Table 4-1. Pin Functions: OPA206 PIN TYPE DESCRIPTION NAME NO.
+IN 3 Input Noninverting input –IN 2 Input Inverting input NC 1, 5, 8 — No internal connection (can be left floating) OUT 6 Output Output V+ 7 Power Positive (highest) power supply V– 4 Power Negative (lowest) power supply OUT A 1 8 V+ 2 ±IN A 7 OUT B +IN A 3 6 ±IN B V 4 ± 5 +IN B Not to scale
Figure 4-2. OPA2206: D Package, 8-pin SOIC and DGK Package, 8-Pin VSSOP (Top View) Table 4-2. Pin Functions: OPA2206 PIN DESCRIPTION NAME NO. TYPE
+IN A 3 Input Noninverting input, channel A –IN A 2 Input Inverting input, channel A +IN B 5 Input Noninverting input, channel B –IN B 6 Input Inverting input, channel B OUT A 1 Output Output, channel A OUT B 7 Output Output, channel B V+ 8 Power Positive (highest) power supply V– 4 Power Negative (lowest) power supply Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: OPA206 OPA2206 OPA4206 Document Outline 1 Features 2 Applications 3 Description Table of Contents 4 Pin Configuration and Functions 5 Specifications 5.1 Absolute Maximum Ratings 5.2 ESD Ratings 5.3 Recommended Operating Conditions 5.4 Thermal Information: OPA206 5.5 Thermal Information: OPA2206 5.6 Thermal Information: OPA4206 5.7 Electrical Characteristics: VS = ±5 V 5.8 Electrical Characteristics: VS = ±15 V 5.9 Typical Characteristics 6 Parameter Measurement Information 6.1 Typical Specifications and Distributions 7 Detailed Description 7.1 Overview 7.2 Functional Block Diagram 7.3 Feature Description 7.3.1 Input Overvoltage Protection 7.3.2 Input Offset Trimming 7.3.3 Lower Input Bias With Super-Beta Inputs 7.3.4 Overload Power Limiter 7.3.5 EMI Rejection 7.4 Device Functional Modes 8 Application and Implementation 8.1 Application Information 8.2 Typical Applications 8.2.1 Voltage Attenuator 8.2.1.1 Design Requirements 8.2.1.2 Detailed Design Procedure 8.2.1.3 Application Curves 8.2.2 Discrete, Two-Op-Amp Instrumentation Amplifier 8.2.3 Input Buffer and Protection for ADC Driver 8.3 Power Supply Recommendations 8.4 Layout 8.4.1 Layout Guidelines 8.4.2 Layout Example 9 Device and Documentation Support 9.1 Device Support 9.1.1 Development Support 9.1.1.1 PSpice® for TI 9.2 Documentation Support 9.2.1 Related Documentation 9.3 Receiving Notification of Documentation Updates 9.4 Support Resources 9.5 Trademarks 9.6 Electrostatic Discharge Caution 9.7 Glossary 10 Revision History 11 Mechanical, Packaging, and Orderable Information
SBOSA11E – MARCH 2020 – REVISED DECEMBER 2023
4 Pin Configuration and Functions
NC 1 8 NC 2 ±IN ± 7 V+ +IN 3 + 6 OUT V 4 ± 5 NC Not to scale
Figure 4-1. OPA206: D Package, 8-Pin SOIC (Top View) Table 4-1. Pin Functions: OPA206 PIN TYPE DESCRIPTION NAME NO.
+IN 3 Input Noninverting input –IN 2 Input Inverting input NC 1, 5, 8 — No internal connection (can be left floating) OUT 6 Output Output V+ 7 Power Positive (highest) power supply V– 4 Power Negative (lowest) power supply OUT A 1 8 V+ 2 ±IN A 7 OUT B +IN A 3 6 ±IN B V 4 ± 5 +IN B Not to scale
Figure 4-2. OPA2206: D Package, 8-pin SOIC and DGK Package, 8-Pin VSSOP (Top View) Table 4-2. Pin Functions: OPA2206 PIN DESCRIPTION NAME NO. TYPE
+IN A 3 Input Noninverting input, channel A –IN A 2 Input Inverting input, channel A +IN B 5 Input Noninverting input, channel B –IN B 6 Input Inverting input, channel B OUT A 1 Output Output, channel A OUT B 7 Output Output, channel B V+ 8 Power Positive (highest) power supply V– 4 Power Negative (lowest) power supply Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: OPA206 OPA2206 OPA4206 Document Outline 1 Features 2 Applications 3 Description Table of Contents 4 Pin Configuration and Functions 5 Specifications 5.1 Absolute Maximum Ratings 5.2 ESD Ratings 5.3 Recommended Operating Conditions 5.4 Thermal Information: OPA206 5.5 Thermal Information: OPA2206 5.6 Thermal Information: OPA4206 5.7 Electrical Characteristics: VS = ±5 V 5.8 Electrical Characteristics: VS = ±15 V 5.9 Typical Characteristics 6 Parameter Measurement Information 6.1 Typical Specifications and Distributions 7 Detailed Description 7.1 Overview 7.2 Functional Block Diagram 7.3 Feature Description 7.3.1 Input Overvoltage Protection 7.3.2 Input Offset Trimming 7.3.3 Lower Input Bias With Super-Beta Inputs 7.3.4 Overload Power Limiter 7.3.5 EMI Rejection 7.4 Device Functional Modes 8 Application and Implementation 8.1 Application Information 8.2 Typical Applications 8.2.1 Voltage Attenuator 8.2.1.1 Design Requirements 8.2.1.2 Detailed Design Procedure 8.2.1.3 Application Curves 8.2.2 Discrete, Two-Op-Amp Instrumentation Amplifier 8.2.3 Input Buffer and Protection for ADC Driver 8.3 Power Supply Recommendations 8.4 Layout 8.4.1 Layout Guidelines 8.4.2 Layout Example 9 Device and Documentation Support 9.1 Device Support 9.1.1 Development Support 9.1.1.1 PSpice® for TI 9.2 Documentation Support 9.2.1 Related Documentation 9.3 Receiving Notification of Documentation Updates 9.4 Support Resources 9.5 Trademarks 9.6 Electrostatic Discharge Caution 9.7 Glossary 10 Revision History 11 Mechanical, Packaging, and Orderable Information