Datasheet nRF51822 - 4
| 描述 | Multiprotocol Bluetooth low energy/2.4 GHz RF System on Chip |
| 页数 / 页 | 115 / 4 — Date. Version. Description. Added content:. Section 8.5.3 “Radio current … |
| 文件格式/大小 | PDF / 7.1 Mb |
| 文件语言 | 英语 |
Date. Version. Description. Added content:. Section 8.5.3 “Radio current consumption with DC/DC enabled”
文件文字版本
link to page 50 link to page 77 link to page 10 link to page 21 link to page 21 link to page 22 link to page 23 link to page 27 link to page 30 link to page 32 link to page 36 link to page 38 link to page 40 link to page 41 link to page 42 link to page 43 link to page 43 link to page 44 link to page 48 link to page 48 link to page 54 link to page 54 link to page 55 link to page 55 link to page 56 link to page 60 link to page 61 link to page 61 link to page 64 link to page 65 link to page 67 link to page 75 link to page 76 nRF51822 Product Specification v3.1
Date Version Description
August 2014 3.0 Update to reflect the changes in build code: • nRF51822-QFAA Hx0 • nRF51822-CEAA Ex0 • nRF51822-QFAB Cx0 (The x in the build codes can be any number between 0 and 9.) If you are working with a previous revision of the chip, read version 2.x of the document.
Added content:
•
Section 8.5.3 “Radio current consumption with DC/DC enabled”
on page 50 •
Section 11.1.1 “PCB layout example”
on page 77
Updated content:
• Feature list on the front page. •
Section 2.1 “Block diagram”
on page 10 •
Section 3.2.1 “Code organization”
on page 21 •
Section 3.2.2 “RAM organization”
on page 21 •
Section 3.3 “Memory Protection Unit (MPU)”
on page 22 •
Section 3.4 “Power management (POWER)”
on page 23 •
Section 3.6 “Clock management (CLOCK)”
on page 27 •
Section 3.8 “Debugger support”
on page 30 •
Section 4.2 “Timer/counters (TIMER)”
on page 32 •
Chapter 5 “Instance table”
on page 36 •
Chapter 7 “Operating conditions”
on page 38 •
Section 8.1.2 “16 MHz crystal oscillator (16M XOSC)”
on page 40 •
Section 8.1.3 “32 MHz crystal oscillator (32M XOSC)”
on page 41 •
Section 8.1.4 “16 MHz RC oscillator (16M RCOSC)”
on page 42 •
Section 8.1.6 “32.768 kHz RC oscillator (32k RCOSC)”
on page 43 •
Section 8.1.7 “32.768 kHz Synthesized oscillator (32k SYNT)”
on page 43 •
Section 8.2 “Power management”
on page 44 •
Section 8.3 “Block resource requirements”
on page 48 •
Section 8.4 “CPU”
on page 48 •
Section 8.5.6 “Radio timing parameters”
on page 54 •
Section 8.5.7 “Antenna matching network requirements”
on page 54 •
Section 8.7 “Universal Asynchronous Receiver/Transmitter (UART) specifications”
on page 55 •
Section 8.8 “Serial Peripheral Interface Slave (SPIS) specifications”
on page 56 •
Section 8.12 “Analog to Digital Converter (ADC) specifications”
on page 60 •
Section 8.13 “Timer (TIMER) specifications”
on page 61 •
Section 8.15 “Temperature sensor (TEMP)”
on page 61 •
Section 8.22 “Non-Volatile Memory Controller (NVMC) specifications”
on page 64 •
Section 8.24 “Low Power Comparator (LPCOMP) specifications”
on page 65 •
Section 9.2 “CDAB WLCSP package”
on page 67 •
Section 10.7.2 “Development tools”
on page 75 •
Chapter 11 “Reference circuitry”
on page 76 Page 4 Document Outline 1 Introduction 1.1 Required reading 1.2 Writing conventions 2 Product overview 2.1 Block diagram 2.2 Pin assignments and functions 2.2.1 Pin assignment QFN48 2.2.2 CDAB WLCSP ball assignment and functions 2.2.3 CEAA and CFAC WLCSP ball assignment and functions 3 System blocks 3.1 CPU 3.2 Memory 3.2.1 Code organization 3.2.2 RAM organization 3.3 Memory Protection Unit (MPU) 3.4 Power management (POWER) 3.4.1 Power supply 3.4.2 Power management 3.5 Programmable Peripheral Interconnect (PPI) 3.6 Clock management (CLOCK) 3.6.1 16/32 MHz crystal oscillator 3.6.2 32.768 kHz crystal oscillator 3.6.3 32.768 kHz RC oscillator 3.6.4 Synthesized 32.768 kHz clock 3.7 GPIO 3.8 Debugger support 4 Peripheral blocks 4.1 2.4 GHz radio (RADIO) 4.2 Timer/counters (TIMER) 4.3 Real Time Counter (RTC) 4.4 AES Electronic Codebook Mode Encryption (ECB) 4.5 AES CCM Mode Encryption (CCM) 4.6 Accelerated Address Resolver (AAR) 4.7 Random Number Generator (RNG) 4.8 Watchdog Timer (WDT) 4.9 Temperature sensor (TEMP) 4.10 Serial Peripheral Interface (SPI/SPIS) 4.11 Two-wire interface (TWI) 4.12 Universal Asynchronous Receiver/Transmitter (UART) 4.13 Quadrature Decoder (QDEC) 4.14 Analog to Digital Converter (ADC) 4.15 GPIO Task Event blocks (GPIOTE) 4.16 Low Power Comparator (LPCOMP) 5 Instance table 6 Absolute maximum ratings 7 Operating conditions 7.1 WLCSP light sensitivity 8 Electrical specifications 8.1 Clock sources 8.1.1 16/32 MHz crystal startup 8.1.2 16 MHz crystal oscillator (16M XOSC) 8.1.3 32 MHz crystal oscillator (32M XOSC) 8.1.4 16 MHz RC oscillator (16M RCOSC) 8.1.5 32.768 kHz crystal oscillator (32k XOSC) 8.1.6 32.768 kHz RC oscillator (32k RCOSC) 8.1.7 32.768 kHz Synthesized oscillator (32k SYNT) 8.2 Power management 8.3 Block resource requirements 8.4 CPU 8.5 Radio transceiver 8.5.1 General radio characteristics 8.5.2 Radio current consumption with DC/DC disabled 8.5.3 Radio current consumption with DC/DC enabled 8.5.4 Transmitter specifications 8.5.5 Receiver specifications 8.5.6 Radio timing parameters 8.5.7 Antenna matching network requirements 8.6 Received Signal Strength Indicator (RSSI) specifications 8.7 Universal Asynchronous Receiver/Transmitter (UART) specifications 8.8 Serial Peripheral Interface Slave (SPIS) specifications 8.9 Serial Peripheral Interface (SPI) Master specifications 8.10 I2C compatible Two Wire Interface (TWI) specifications 8.11 GPIO Tasks and Events (GPIOTE) specifications 8.12 Analog to Digital Converter (ADC) specifications 8.13 Timer (TIMER) specifications 8.14 Real Time Counter (RTC) 8.15 Temperature sensor (TEMP) 8.16 Random Number Generator (RNG) specifications 8.17 AES Electronic Codebook Mode Encryption (ECB) specifications 8.18 AES CCM Mode Encryption (CCM) specifications 8.19 Accelerated Address Resolver (AAR) specifications 8.20 Watchdog Timer (WDT) specifications 8.21 Quadrature Decoder (QDEC) specifications 8.22 Non-Volatile Memory Controller (NVMC) specifications 8.23 General Purpose I/O (GPIO) specifications 8.24 Low Power Comparator (LPCOMP) specifications 9 Mechanical specifications 9.1 QFN48 package 9.2 CDAB WLCSP package 9.3 CEAA WLCSP package 9.4 CFAC WLCSP package 10 Ordering information 10.1 Chip marking 10.2 Inner box label 10.3 Outer box label 10.4 Order code 10.5 Abbreviations 10.6 Code ranges and values 10.7 Product options 10.7.1 nRF ICs 10.7.2 Development tools 11 Reference circuitry 11.1 PCB guidelines 11.1.1 PCB layout example 11.2 Reference design schematics 11.3 QFAA QFN48 package 11.3.1 QFAA QFN48 schematic with internal LDO setup 11.3.2 QFAA QFN48 schematic with low voltage mode setup 11.3.3 QFAA QFN48 schematic with DC/DC converter setup 11.4 QFAB QFN48 package 11.4.1 QFAB QFN48 schematic with internal LDO setup 11.4.2 QFAB QFN48 schematic with low voltage mode setup 11.4.3 QFAB QFN48 schematic with DC/DC converter setup 11.5 QFAC QFN48 package 11.5.1 QFAC QFN48 schematic with internal LDO setup 11.5.2 QFAC QFN48 schematic with low voltage mode setup 11.5.3 QFAC QFN48 schematic with DC/DC converter setup 11.6 CDAB WLCSP package 11.6.1 CDAB WLCSP schematic with internal LDO setup 11.6.2 CDAB WLCSP schematic with low voltage mode setup 11.6.3 CDAB WLCSP schematic with DC/DC converter setup 11.7 CEAA WLCSP package 11.7.1 CEAA WLCSP schematic with internal LDO setup 11.7.2 CEAA WLCSP schematic with low voltage mode setup 11.7.3 CEAA WLCSP schematic with DC/DC converter setup 11.8 CFAC WLCSP package 11.8.1 CFAC WLCSP schematic with internal LDO setup 11.8.2 CFAC WLCSP schematic with low voltage mode setup 11.8.3 CFAC WLCSP schematic with DC/DC converter setup 12 Glossary
Date Version Description
August 2014 3.0 Update to reflect the changes in build code: • nRF51822-QFAA Hx0 • nRF51822-CEAA Ex0 • nRF51822-QFAB Cx0 (The x in the build codes can be any number between 0 and 9.) If you are working with a previous revision of the chip, read version 2.x of the document.
Added content:
•
Section 8.5.3 “Radio current consumption with DC/DC enabled”
on page 50 •
Section 11.1.1 “PCB layout example”
on page 77
Updated content:
• Feature list on the front page. •
Section 2.1 “Block diagram”
on page 10 •
Section 3.2.1 “Code organization”
on page 21 •
Section 3.2.2 “RAM organization”
on page 21 •
Section 3.3 “Memory Protection Unit (MPU)”
on page 22 •
Section 3.4 “Power management (POWER)”
on page 23 •
Section 3.6 “Clock management (CLOCK)”
on page 27 •
Section 3.8 “Debugger support”
on page 30 •
Section 4.2 “Timer/counters (TIMER)”
on page 32 •
Chapter 5 “Instance table”
on page 36 •
Chapter 7 “Operating conditions”
on page 38 •
Section 8.1.2 “16 MHz crystal oscillator (16M XOSC)”
on page 40 •
Section 8.1.3 “32 MHz crystal oscillator (32M XOSC)”
on page 41 •
Section 8.1.4 “16 MHz RC oscillator (16M RCOSC)”
on page 42 •
Section 8.1.6 “32.768 kHz RC oscillator (32k RCOSC)”
on page 43 •
Section 8.1.7 “32.768 kHz Synthesized oscillator (32k SYNT)”
on page 43 •
Section 8.2 “Power management”
on page 44 •
Section 8.3 “Block resource requirements”
on page 48 •
Section 8.4 “CPU”
on page 48 •
Section 8.5.6 “Radio timing parameters”
on page 54 •
Section 8.5.7 “Antenna matching network requirements”
on page 54 •
Section 8.7 “Universal Asynchronous Receiver/Transmitter (UART) specifications”
on page 55 •
Section 8.8 “Serial Peripheral Interface Slave (SPIS) specifications”
on page 56 •
Section 8.12 “Analog to Digital Converter (ADC) specifications”
on page 60 •
Section 8.13 “Timer (TIMER) specifications”
on page 61 •
Section 8.15 “Temperature sensor (TEMP)”
on page 61 •
Section 8.22 “Non-Volatile Memory Controller (NVMC) specifications”
on page 64 •
Section 8.24 “Low Power Comparator (LPCOMP) specifications”
on page 65 •
Section 9.2 “CDAB WLCSP package”
on page 67 •
Section 10.7.2 “Development tools”
on page 75 •
Chapter 11 “Reference circuitry”
on page 76 Page 4 Document Outline 1 Introduction 1.1 Required reading 1.2 Writing conventions 2 Product overview 2.1 Block diagram 2.2 Pin assignments and functions 2.2.1 Pin assignment QFN48 2.2.2 CDAB WLCSP ball assignment and functions 2.2.3 CEAA and CFAC WLCSP ball assignment and functions 3 System blocks 3.1 CPU 3.2 Memory 3.2.1 Code organization 3.2.2 RAM organization 3.3 Memory Protection Unit (MPU) 3.4 Power management (POWER) 3.4.1 Power supply 3.4.2 Power management 3.5 Programmable Peripheral Interconnect (PPI) 3.6 Clock management (CLOCK) 3.6.1 16/32 MHz crystal oscillator 3.6.2 32.768 kHz crystal oscillator 3.6.3 32.768 kHz RC oscillator 3.6.4 Synthesized 32.768 kHz clock 3.7 GPIO 3.8 Debugger support 4 Peripheral blocks 4.1 2.4 GHz radio (RADIO) 4.2 Timer/counters (TIMER) 4.3 Real Time Counter (RTC) 4.4 AES Electronic Codebook Mode Encryption (ECB) 4.5 AES CCM Mode Encryption (CCM) 4.6 Accelerated Address Resolver (AAR) 4.7 Random Number Generator (RNG) 4.8 Watchdog Timer (WDT) 4.9 Temperature sensor (TEMP) 4.10 Serial Peripheral Interface (SPI/SPIS) 4.11 Two-wire interface (TWI) 4.12 Universal Asynchronous Receiver/Transmitter (UART) 4.13 Quadrature Decoder (QDEC) 4.14 Analog to Digital Converter (ADC) 4.15 GPIO Task Event blocks (GPIOTE) 4.16 Low Power Comparator (LPCOMP) 5 Instance table 6 Absolute maximum ratings 7 Operating conditions 7.1 WLCSP light sensitivity 8 Electrical specifications 8.1 Clock sources 8.1.1 16/32 MHz crystal startup 8.1.2 16 MHz crystal oscillator (16M XOSC) 8.1.3 32 MHz crystal oscillator (32M XOSC) 8.1.4 16 MHz RC oscillator (16M RCOSC) 8.1.5 32.768 kHz crystal oscillator (32k XOSC) 8.1.6 32.768 kHz RC oscillator (32k RCOSC) 8.1.7 32.768 kHz Synthesized oscillator (32k SYNT) 8.2 Power management 8.3 Block resource requirements 8.4 CPU 8.5 Radio transceiver 8.5.1 General radio characteristics 8.5.2 Radio current consumption with DC/DC disabled 8.5.3 Radio current consumption with DC/DC enabled 8.5.4 Transmitter specifications 8.5.5 Receiver specifications 8.5.6 Radio timing parameters 8.5.7 Antenna matching network requirements 8.6 Received Signal Strength Indicator (RSSI) specifications 8.7 Universal Asynchronous Receiver/Transmitter (UART) specifications 8.8 Serial Peripheral Interface Slave (SPIS) specifications 8.9 Serial Peripheral Interface (SPI) Master specifications 8.10 I2C compatible Two Wire Interface (TWI) specifications 8.11 GPIO Tasks and Events (GPIOTE) specifications 8.12 Analog to Digital Converter (ADC) specifications 8.13 Timer (TIMER) specifications 8.14 Real Time Counter (RTC) 8.15 Temperature sensor (TEMP) 8.16 Random Number Generator (RNG) specifications 8.17 AES Electronic Codebook Mode Encryption (ECB) specifications 8.18 AES CCM Mode Encryption (CCM) specifications 8.19 Accelerated Address Resolver (AAR) specifications 8.20 Watchdog Timer (WDT) specifications 8.21 Quadrature Decoder (QDEC) specifications 8.22 Non-Volatile Memory Controller (NVMC) specifications 8.23 General Purpose I/O (GPIO) specifications 8.24 Low Power Comparator (LPCOMP) specifications 9 Mechanical specifications 9.1 QFN48 package 9.2 CDAB WLCSP package 9.3 CEAA WLCSP package 9.4 CFAC WLCSP package 10 Ordering information 10.1 Chip marking 10.2 Inner box label 10.3 Outer box label 10.4 Order code 10.5 Abbreviations 10.6 Code ranges and values 10.7 Product options 10.7.1 nRF ICs 10.7.2 Development tools 11 Reference circuitry 11.1 PCB guidelines 11.1.1 PCB layout example 11.2 Reference design schematics 11.3 QFAA QFN48 package 11.3.1 QFAA QFN48 schematic with internal LDO setup 11.3.2 QFAA QFN48 schematic with low voltage mode setup 11.3.3 QFAA QFN48 schematic with DC/DC converter setup 11.4 QFAB QFN48 package 11.4.1 QFAB QFN48 schematic with internal LDO setup 11.4.2 QFAB QFN48 schematic with low voltage mode setup 11.4.3 QFAB QFN48 schematic with DC/DC converter setup 11.5 QFAC QFN48 package 11.5.1 QFAC QFN48 schematic with internal LDO setup 11.5.2 QFAC QFN48 schematic with low voltage mode setup 11.5.3 QFAC QFN48 schematic with DC/DC converter setup 11.6 CDAB WLCSP package 11.6.1 CDAB WLCSP schematic with internal LDO setup 11.6.2 CDAB WLCSP schematic with low voltage mode setup 11.6.3 CDAB WLCSP schematic with DC/DC converter setup 11.7 CEAA WLCSP package 11.7.1 CEAA WLCSP schematic with internal LDO setup 11.7.2 CEAA WLCSP schematic with low voltage mode setup 11.7.3 CEAA WLCSP schematic with DC/DC converter setup 11.8 CFAC WLCSP package 11.8.1 CFAC WLCSP schematic with internal LDO setup 11.8.2 CFAC WLCSP schematic with low voltage mode setup 11.8.3 CFAC WLCSP schematic with DC/DC converter setup 12 Glossary