Datasheet nRF51822 - 5
| 描述 | Multiprotocol Bluetooth low energy/2.4 GHz RF System on Chip |
| 页数 / 页 | 115 / 5 — Date. Version. Description. Updated. Chapter 1 “Introduction”. Section … |
| 文件格式/大小 | PDF / 7.1 Mb |
| 文件语言 | 英语 |
Date. Version. Description. Updated. Chapter 1 “Introduction”. Section 2.1 “Block diagram”
文件文字版本
link to page 9 link to page 10 link to page 11 link to page 20 link to page 26 link to page 30 link to page 31 link to page 32 link to page 32 link to page 34 link to page 35 link to page 35 link to page 35 link to page 36 link to page 37 link to page 39 link to page 39 link to page 40 link to page 41 link to page 44 link to page 48 link to page 55 link to page 55 link to page 57 link to page 59 link to page 61 link to page 62 link to page 62 link to page 62 link to page 62 link to page 63 link to page 76 link to page 79 link to page 103 link to page 22 link to page 33 link to page 33 link to page 35 link to page 54 link to page 56 link to page 62 link to page 62 link to page 65 nRF51822 Product Specification v3.1
Date Version Description
October 2013 2.0 This version of the document will target the nRF51822 QFAA G0 revision of the chip. If you are working with a previous revision of the chip, read version 1.3 or earlier of the document.
Updated
the following sections: Key Feature list on the front page,
Chapter 1 “Introduction”
on page 9,
Section 2.1 “Block diagram”
on page 10,
Section 2.2 “Pin assignments and functions”
on page 11,
Section 3.2 “Memory”
on page 20,
Section 3.5 “Programmable Peripheral Interconnect (PPI)”
on page 26,
Section 3.7 “GPIO”
on page 30,
Section 4.1 “2.4 GHz radio (RADIO)”
on page 31,
Section 4.2 “Timer/counters (TIMER)”
on page 32,
Section 4.3 “Real Time Counter (RTC)”
on page 32,
Section 4.10 “Serial Peripheral Interface (SPI/SPIS)”
on page 34,
Section 4.12 “Universal Asynchronous Receiver/Transmitter (UART)”
on page 35,
Section 4.14 “Analog to Digital Converter (ADC)”
on page 35,
Section 4.15 “GPIO Task Event blocks (GPIOTE)”
on page 35,
Chapter 5 “Instance table”
on page 36,
Chapter 6 “Absolute maximum ratings”
on page 37,
Chapter 8 “Electrical specifications”
on page 39,
Section 8.1 “Clock sources”
on page 39,
Section 8.1.2 “16 MHz crystal oscillator (16M XOSC)”
on page 40,
Section 8.1.3 “32 MHz crystal oscillator (32M XOSC)”
on page 41,
Section 8.2 “Power management”
on page 44,
Section 8.3 “Block resource requirements”
on page 48,
Section 8.7 “Universal Asynchronous Receiver/Transmitter (UART) specifications”
on page 55,
Section 8.9 “Serial Peripheral Interface (SPI) Master specifications”
on page 57,
Section 8.11 “GPIO Tasks and Events (GPIOTE) specifications”
on page 59,
Section 8.13 “Timer (TIMER) specifications”
on page 61,
Section 8.16 “Random Number Generator (RNG) specifications”
on page 62,
Section 8.17 “AES Electronic Codebook Mode Encryption (ECB) specifications”
on page 62,
Section 8.18 “AES CCM Mode Encryption (CCM) specifications”
on page 62,
Section 8.19 “Accelerated Address Resolver (AAR) specifications”
on page 62,
Section 8.21 “Quadrature Decoder (QDEC) specifications”
on page 63,
Section 11.1 “PCB guidelines”
on page 76,
Section 11.3 “QFAA QFN48 package”
on page 79, and
Section 11.7 “CEAA WLCSP package”
on page 103.
Added
the following sections:
Section 3.3 “Memory Protection Unit (MPU)”
on page 22,
Section 4.5 “AES CCM Mode Encryption (CCM)”
on page 33,
Section 4.6 “Accelerated Address Resolver (AAR)”
on page 33,
Section 4.16 “Low Power Comparator (LPCOMP)”
on page 35,
Section 8.5.7 “Antenna matching network requirements”
on page 54,
Section 8.8 “Serial Peripheral Interface Slave (SPIS) specifications”
on page 56,
Section 8.18 “AES CCM Mode Encryption (CCM) specifications”
on page 62,
Section 8.19 “Accelerated Address Resolver (AAR) specifications”
on page 62, and
Section 8.24 “Low Power Comparator (LPCOMP) specifications”
on page 65. May 2013 1.3 Updated schematics and BOMs in section 11.3 on page 61. Page 5 Document Outline 1 Introduction 1.1 Required reading 1.2 Writing conventions 2 Product overview 2.1 Block diagram 2.2 Pin assignments and functions 2.2.1 Pin assignment QFN48 2.2.2 CDAB WLCSP ball assignment and functions 2.2.3 CEAA and CFAC WLCSP ball assignment and functions 3 System blocks 3.1 CPU 3.2 Memory 3.2.1 Code organization 3.2.2 RAM organization 3.3 Memory Protection Unit (MPU) 3.4 Power management (POWER) 3.4.1 Power supply 3.4.2 Power management 3.5 Programmable Peripheral Interconnect (PPI) 3.6 Clock management (CLOCK) 3.6.1 16/32 MHz crystal oscillator 3.6.2 32.768 kHz crystal oscillator 3.6.3 32.768 kHz RC oscillator 3.6.4 Synthesized 32.768 kHz clock 3.7 GPIO 3.8 Debugger support 4 Peripheral blocks 4.1 2.4 GHz radio (RADIO) 4.2 Timer/counters (TIMER) 4.3 Real Time Counter (RTC) 4.4 AES Electronic Codebook Mode Encryption (ECB) 4.5 AES CCM Mode Encryption (CCM) 4.6 Accelerated Address Resolver (AAR) 4.7 Random Number Generator (RNG) 4.8 Watchdog Timer (WDT) 4.9 Temperature sensor (TEMP) 4.10 Serial Peripheral Interface (SPI/SPIS) 4.11 Two-wire interface (TWI) 4.12 Universal Asynchronous Receiver/Transmitter (UART) 4.13 Quadrature Decoder (QDEC) 4.14 Analog to Digital Converter (ADC) 4.15 GPIO Task Event blocks (GPIOTE) 4.16 Low Power Comparator (LPCOMP) 5 Instance table 6 Absolute maximum ratings 7 Operating conditions 7.1 WLCSP light sensitivity 8 Electrical specifications 8.1 Clock sources 8.1.1 16/32 MHz crystal startup 8.1.2 16 MHz crystal oscillator (16M XOSC) 8.1.3 32 MHz crystal oscillator (32M XOSC) 8.1.4 16 MHz RC oscillator (16M RCOSC) 8.1.5 32.768 kHz crystal oscillator (32k XOSC) 8.1.6 32.768 kHz RC oscillator (32k RCOSC) 8.1.7 32.768 kHz Synthesized oscillator (32k SYNT) 8.2 Power management 8.3 Block resource requirements 8.4 CPU 8.5 Radio transceiver 8.5.1 General radio characteristics 8.5.2 Radio current consumption with DC/DC disabled 8.5.3 Radio current consumption with DC/DC enabled 8.5.4 Transmitter specifications 8.5.5 Receiver specifications 8.5.6 Radio timing parameters 8.5.7 Antenna matching network requirements 8.6 Received Signal Strength Indicator (RSSI) specifications 8.7 Universal Asynchronous Receiver/Transmitter (UART) specifications 8.8 Serial Peripheral Interface Slave (SPIS) specifications 8.9 Serial Peripheral Interface (SPI) Master specifications 8.10 I2C compatible Two Wire Interface (TWI) specifications 8.11 GPIO Tasks and Events (GPIOTE) specifications 8.12 Analog to Digital Converter (ADC) specifications 8.13 Timer (TIMER) specifications 8.14 Real Time Counter (RTC) 8.15 Temperature sensor (TEMP) 8.16 Random Number Generator (RNG) specifications 8.17 AES Electronic Codebook Mode Encryption (ECB) specifications 8.18 AES CCM Mode Encryption (CCM) specifications 8.19 Accelerated Address Resolver (AAR) specifications 8.20 Watchdog Timer (WDT) specifications 8.21 Quadrature Decoder (QDEC) specifications 8.22 Non-Volatile Memory Controller (NVMC) specifications 8.23 General Purpose I/O (GPIO) specifications 8.24 Low Power Comparator (LPCOMP) specifications 9 Mechanical specifications 9.1 QFN48 package 9.2 CDAB WLCSP package 9.3 CEAA WLCSP package 9.4 CFAC WLCSP package 10 Ordering information 10.1 Chip marking 10.2 Inner box label 10.3 Outer box label 10.4 Order code 10.5 Abbreviations 10.6 Code ranges and values 10.7 Product options 10.7.1 nRF ICs 10.7.2 Development tools 11 Reference circuitry 11.1 PCB guidelines 11.1.1 PCB layout example 11.2 Reference design schematics 11.3 QFAA QFN48 package 11.3.1 QFAA QFN48 schematic with internal LDO setup 11.3.2 QFAA QFN48 schematic with low voltage mode setup 11.3.3 QFAA QFN48 schematic with DC/DC converter setup 11.4 QFAB QFN48 package 11.4.1 QFAB QFN48 schematic with internal LDO setup 11.4.2 QFAB QFN48 schematic with low voltage mode setup 11.4.3 QFAB QFN48 schematic with DC/DC converter setup 11.5 QFAC QFN48 package 11.5.1 QFAC QFN48 schematic with internal LDO setup 11.5.2 QFAC QFN48 schematic with low voltage mode setup 11.5.3 QFAC QFN48 schematic with DC/DC converter setup 11.6 CDAB WLCSP package 11.6.1 CDAB WLCSP schematic with internal LDO setup 11.6.2 CDAB WLCSP schematic with low voltage mode setup 11.6.3 CDAB WLCSP schematic with DC/DC converter setup 11.7 CEAA WLCSP package 11.7.1 CEAA WLCSP schematic with internal LDO setup 11.7.2 CEAA WLCSP schematic with low voltage mode setup 11.7.3 CEAA WLCSP schematic with DC/DC converter setup 11.8 CFAC WLCSP package 11.8.1 CFAC WLCSP schematic with internal LDO setup 11.8.2 CFAC WLCSP schematic with low voltage mode setup 11.8.3 CFAC WLCSP schematic with DC/DC converter setup 12 Glossary
Date Version Description
October 2013 2.0 This version of the document will target the nRF51822 QFAA G0 revision of the chip. If you are working with a previous revision of the chip, read version 1.3 or earlier of the document.
Updated
the following sections: Key Feature list on the front page,
Chapter 1 “Introduction”
on page 9,
Section 2.1 “Block diagram”
on page 10,
Section 2.2 “Pin assignments and functions”
on page 11,
Section 3.2 “Memory”
on page 20,
Section 3.5 “Programmable Peripheral Interconnect (PPI)”
on page 26,
Section 3.7 “GPIO”
on page 30,
Section 4.1 “2.4 GHz radio (RADIO)”
on page 31,
Section 4.2 “Timer/counters (TIMER)”
on page 32,
Section 4.3 “Real Time Counter (RTC)”
on page 32,
Section 4.10 “Serial Peripheral Interface (SPI/SPIS)”
on page 34,
Section 4.12 “Universal Asynchronous Receiver/Transmitter (UART)”
on page 35,
Section 4.14 “Analog to Digital Converter (ADC)”
on page 35,
Section 4.15 “GPIO Task Event blocks (GPIOTE)”
on page 35,
Chapter 5 “Instance table”
on page 36,
Chapter 6 “Absolute maximum ratings”
on page 37,
Chapter 8 “Electrical specifications”
on page 39,
Section 8.1 “Clock sources”
on page 39,
Section 8.1.2 “16 MHz crystal oscillator (16M XOSC)”
on page 40,
Section 8.1.3 “32 MHz crystal oscillator (32M XOSC)”
on page 41,
Section 8.2 “Power management”
on page 44,
Section 8.3 “Block resource requirements”
on page 48,
Section 8.7 “Universal Asynchronous Receiver/Transmitter (UART) specifications”
on page 55,
Section 8.9 “Serial Peripheral Interface (SPI) Master specifications”
on page 57,
Section 8.11 “GPIO Tasks and Events (GPIOTE) specifications”
on page 59,
Section 8.13 “Timer (TIMER) specifications”
on page 61,
Section 8.16 “Random Number Generator (RNG) specifications”
on page 62,
Section 8.17 “AES Electronic Codebook Mode Encryption (ECB) specifications”
on page 62,
Section 8.18 “AES CCM Mode Encryption (CCM) specifications”
on page 62,
Section 8.19 “Accelerated Address Resolver (AAR) specifications”
on page 62,
Section 8.21 “Quadrature Decoder (QDEC) specifications”
on page 63,
Section 11.1 “PCB guidelines”
on page 76,
Section 11.3 “QFAA QFN48 package”
on page 79, and
Section 11.7 “CEAA WLCSP package”
on page 103.
Added
the following sections:
Section 3.3 “Memory Protection Unit (MPU)”
on page 22,
Section 4.5 “AES CCM Mode Encryption (CCM)”
on page 33,
Section 4.6 “Accelerated Address Resolver (AAR)”
on page 33,
Section 4.16 “Low Power Comparator (LPCOMP)”
on page 35,
Section 8.5.7 “Antenna matching network requirements”
on page 54,
Section 8.8 “Serial Peripheral Interface Slave (SPIS) specifications”
on page 56,
Section 8.18 “AES CCM Mode Encryption (CCM) specifications”
on page 62,
Section 8.19 “Accelerated Address Resolver (AAR) specifications”
on page 62, and
Section 8.24 “Low Power Comparator (LPCOMP) specifications”
on page 65. May 2013 1.3 Updated schematics and BOMs in section 11.3 on page 61. Page 5 Document Outline 1 Introduction 1.1 Required reading 1.2 Writing conventions 2 Product overview 2.1 Block diagram 2.2 Pin assignments and functions 2.2.1 Pin assignment QFN48 2.2.2 CDAB WLCSP ball assignment and functions 2.2.3 CEAA and CFAC WLCSP ball assignment and functions 3 System blocks 3.1 CPU 3.2 Memory 3.2.1 Code organization 3.2.2 RAM organization 3.3 Memory Protection Unit (MPU) 3.4 Power management (POWER) 3.4.1 Power supply 3.4.2 Power management 3.5 Programmable Peripheral Interconnect (PPI) 3.6 Clock management (CLOCK) 3.6.1 16/32 MHz crystal oscillator 3.6.2 32.768 kHz crystal oscillator 3.6.3 32.768 kHz RC oscillator 3.6.4 Synthesized 32.768 kHz clock 3.7 GPIO 3.8 Debugger support 4 Peripheral blocks 4.1 2.4 GHz radio (RADIO) 4.2 Timer/counters (TIMER) 4.3 Real Time Counter (RTC) 4.4 AES Electronic Codebook Mode Encryption (ECB) 4.5 AES CCM Mode Encryption (CCM) 4.6 Accelerated Address Resolver (AAR) 4.7 Random Number Generator (RNG) 4.8 Watchdog Timer (WDT) 4.9 Temperature sensor (TEMP) 4.10 Serial Peripheral Interface (SPI/SPIS) 4.11 Two-wire interface (TWI) 4.12 Universal Asynchronous Receiver/Transmitter (UART) 4.13 Quadrature Decoder (QDEC) 4.14 Analog to Digital Converter (ADC) 4.15 GPIO Task Event blocks (GPIOTE) 4.16 Low Power Comparator (LPCOMP) 5 Instance table 6 Absolute maximum ratings 7 Operating conditions 7.1 WLCSP light sensitivity 8 Electrical specifications 8.1 Clock sources 8.1.1 16/32 MHz crystal startup 8.1.2 16 MHz crystal oscillator (16M XOSC) 8.1.3 32 MHz crystal oscillator (32M XOSC) 8.1.4 16 MHz RC oscillator (16M RCOSC) 8.1.5 32.768 kHz crystal oscillator (32k XOSC) 8.1.6 32.768 kHz RC oscillator (32k RCOSC) 8.1.7 32.768 kHz Synthesized oscillator (32k SYNT) 8.2 Power management 8.3 Block resource requirements 8.4 CPU 8.5 Radio transceiver 8.5.1 General radio characteristics 8.5.2 Radio current consumption with DC/DC disabled 8.5.3 Radio current consumption with DC/DC enabled 8.5.4 Transmitter specifications 8.5.5 Receiver specifications 8.5.6 Radio timing parameters 8.5.7 Antenna matching network requirements 8.6 Received Signal Strength Indicator (RSSI) specifications 8.7 Universal Asynchronous Receiver/Transmitter (UART) specifications 8.8 Serial Peripheral Interface Slave (SPIS) specifications 8.9 Serial Peripheral Interface (SPI) Master specifications 8.10 I2C compatible Two Wire Interface (TWI) specifications 8.11 GPIO Tasks and Events (GPIOTE) specifications 8.12 Analog to Digital Converter (ADC) specifications 8.13 Timer (TIMER) specifications 8.14 Real Time Counter (RTC) 8.15 Temperature sensor (TEMP) 8.16 Random Number Generator (RNG) specifications 8.17 AES Electronic Codebook Mode Encryption (ECB) specifications 8.18 AES CCM Mode Encryption (CCM) specifications 8.19 Accelerated Address Resolver (AAR) specifications 8.20 Watchdog Timer (WDT) specifications 8.21 Quadrature Decoder (QDEC) specifications 8.22 Non-Volatile Memory Controller (NVMC) specifications 8.23 General Purpose I/O (GPIO) specifications 8.24 Low Power Comparator (LPCOMP) specifications 9 Mechanical specifications 9.1 QFN48 package 9.2 CDAB WLCSP package 9.3 CEAA WLCSP package 9.4 CFAC WLCSP package 10 Ordering information 10.1 Chip marking 10.2 Inner box label 10.3 Outer box label 10.4 Order code 10.5 Abbreviations 10.6 Code ranges and values 10.7 Product options 10.7.1 nRF ICs 10.7.2 Development tools 11 Reference circuitry 11.1 PCB guidelines 11.1.1 PCB layout example 11.2 Reference design schematics 11.3 QFAA QFN48 package 11.3.1 QFAA QFN48 schematic with internal LDO setup 11.3.2 QFAA QFN48 schematic with low voltage mode setup 11.3.3 QFAA QFN48 schematic with DC/DC converter setup 11.4 QFAB QFN48 package 11.4.1 QFAB QFN48 schematic with internal LDO setup 11.4.2 QFAB QFN48 schematic with low voltage mode setup 11.4.3 QFAB QFN48 schematic with DC/DC converter setup 11.5 QFAC QFN48 package 11.5.1 QFAC QFN48 schematic with internal LDO setup 11.5.2 QFAC QFN48 schematic with low voltage mode setup 11.5.3 QFAC QFN48 schematic with DC/DC converter setup 11.6 CDAB WLCSP package 11.6.1 CDAB WLCSP schematic with internal LDO setup 11.6.2 CDAB WLCSP schematic with low voltage mode setup 11.6.3 CDAB WLCSP schematic with DC/DC converter setup 11.7 CEAA WLCSP package 11.7.1 CEAA WLCSP schematic with internal LDO setup 11.7.2 CEAA WLCSP schematic with low voltage mode setup 11.7.3 CEAA WLCSP schematic with DC/DC converter setup 11.8 CFAC WLCSP package 11.8.1 CFAC WLCSP schematic with internal LDO setup 11.8.2 CFAC WLCSP schematic with low voltage mode setup 11.8.3 CFAC WLCSP schematic with DC/DC converter setup 12 Glossary