Datasheet AD8330 (Analog Devices) - 6

AD8330 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS L T S R NB E OFS VPO CNT 16 15 14 13 PIN 1 VPSI 1 INDICATOR 12 VPSO INHI 2 11 OPHI AD8330 INLO 3 TOP VIEW 10 OPLO (Not to Scale) OFST 1 16 V O P S MODE 4 9 CMOP ENBL 2 15 CNTR 5 6 7 8 P V I S 3 AD8330 14 P V O S N M G INHI 4 TOP VIEW 13 OPHI G DBS M (Not to Scale) V INLO 5 12 OPLO CM CO VMA NOTES MODE 6 11 CMOP 1. THE EXPOSED PAD IS NOT CONNECTED INTERNALLY. FOR INCREASED RELIABILITY OF THE SOLDER JOINTS D V BS 7 10 VM G A
003
AND MAXIMUM THERMAL CAPABILITY, IT IS RECOMMENDED
004
CMGN 8 9 COMM THAT THE PAD BE SOLDERED TO THE GROUND PLANE.
03217- 03217- Figure 2. 16-Lead LFCSP Pin Configuration Figure 3. 16-Lead QSOP Pin Configuration
Table 3. 16-Lead LFCSP Pin Function Descriptions Table 4. 16-Lead QSOP Pin Function Descriptions Pin No. Mnemonic Description Pin No. Mnemonic Description
1 VPSI Positive Supply for Input Stages. 1 OFST Used in Offset Control Modes. 2 INHI Differential Signal Input, Positive 2 ENBL Power Enable, Active High. Polarity. 3 VPSI Positive Supply for Input Stages. 3 INLO Differential Signal Input, Negative 4 INHI Differential Signal Input, Positive Polarity. Polarity. 4 MODE Logic Input: Selects Gain Slope. 5 INLO Differential Signal Input, Negative High = gain up vs. VDBS. Polarity. 5 VDBS Input for Linear-in-dB Gain Control 6 MODE Logic Input: Selects Gain Slope. Voltage, VDBS. High = gain up vs. VDBS. 6 CMGN Common Baseline for Gain Control 7 VDBS Input for linear-in-dB Gain Control Interfaces. Voltage, VDBS. 7 COMM Ground for Input and Gain Control Bias 8 CMGN Common Baseline for Gain Control Circuitry. Interfaces. 8 VMAG Input for Gain/Amplitude Control, VMAG. 9 COMM Ground for Input and Gain Control Bias 9 CMOP Ground for Output Stages. Circuitry. 10 OPLO Differential Signal Output, Negative 10 VMAG Input for Gain/Amplitude Control, VMAG. Polarity. 11 CMOP Ground for Output Stages. 11 OPHI Differential Signal Output, Positive 12 OPLO Differential Signal Output, Negative Polarity. Polarity. 12 VPSO Positive Supply for Output Stages. 13 OPHI Differential Signal Output, Positive 13 CNTR Common-Mode Output Voltage Control. Polarity. 14 VPOS Positive Supply for Inner Stages. 14 VPSO Positive Supply for Output Stages. 15 OFST Used in Offset Control Modes. 15 CNTR Common-Mode Output Voltage Control. 16 ENBL Power Enable, Active High. 16 VPOS Positive Supply for Inner Stages. EPAD Exposed Pad. It is recommended that the pad be soldered to the ground plane. Rev. G | Page 6 of 32 Document Outline Features Applications Functional Block Diagram General Description Table of Contents Revision History Specifications Absolute Maximum Ratings ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Theory of Operation Circuit Description Overall Structure Normal Operating Conditions Linear-in-dB Gain Control (VDBS) Inversion of the Gain Slope Gain Magnitude Control (VMAG) Two Classes of Variable Gain Amplifiers Amplitude/Phase Response Noise, Input Capacity, and Dynamic Range Dynamic Range Input Common-Mode Range and Rejection Ratio Output Noise and Peak Swing Offset Compensation Effects of Loading on Gain and AC Response Gain Errors Due to On-Chip Resistor Tolerances Output (Input) Common-Mode Control Using the AD8330 Gain and Swing Adjustments When Loaded Input Coupling DC-Coupled Signal Path Using Single-Sided Sources and Loads Pulse Operation Preserving Absolute Gain Calculation of Noise Figure Noise as a Function of VDBS Distortion Considerations P1dB and V1dB Applications Information ADC Driving Simple AGC Amplifier Wide Range True RMS Voltmeter Evaluation Board General Description Basic Operation Options Measurement Setup AD8330-EVALZ Board Design Outline Dimensions Ordering Guide