Datasheet MCP6421, MCP6422, MCP6424 (Microchip) - 18

link to page 18 link to page 7 link to page 7 link to page 10 link to page 11 link to page 18 link to page 18
MCP6421/2/4
4.1.4 NORMAL OPERATION The input stage of the MCP6421/2/4 op amps uses two
100000 V = 5.5 V DD
differential input stages in parallel. One operates at a
) R = 100 kȍ (
Ω
L 10000
low Common mode input voltage (VCM), while the other
ISO
operates at a high VCM. With this topology, the device
1000
operates with a VCM up to 300 mV above VDD and
G : N
300 mV below V
1 V/V
SS. The input offset voltage is
100 2 V/V
measured at VCM = VSS – 0.3V and VDD + 0.3V, to
mmended R
≥
o 5 V/V o
ensure proper operation.
10 Rec
The transition between the input stages occurs when
1
VCM is near VDD – 0.6V (see Figures 2-3 and 2-4). For
1.E-11 1.E-10 1.E-09 1.E-08 10p 100p 1n 10n 1.E-07 0.1μ
the best distortion performance and gain linearity, with
Normalized Load Capacitance; C /G (F) L N
non-inverting gains, avoid this region of operation.
FIGURE 4-5:
Recommended RISO Values
4.2 Rail-to-Rail Output
for Capacitive Loads. The output voltage range of the MCP6421/2/4 op amps After selecting RISO for your circuit, double-check the is 0.001V (typical) and 5.499V (typical) when resulting frequency response peaking and step R response overshoot. Modify RISO’s value until the L = 100 k is connected to VDD/2 and VDD = 5.5V. Refer to Figures 2-24 and 2-26 for more information. response is reasonable. Bench evaluation and simulations with the MCP6421/2/4 SPICE macro model are very helpful.
4.3 Capacitive Loads
Driving large capacitive loads can cause stability
4.4 Supply Bypass
problems for voltage feedback op amps. As the load capacitance increases, the feedback loop’s phase The MCP6421/2/4 op amps’ power supply pin (VDD for margin decreases, and the closed-loop bandwidth is single-supply) should have a local bypass capacitor reduced. This produces gain peaking in the frequency (i.e., 0.01 µF to 0.1 µF) within 2 mm for good high response, with overshoot and ringing in the step frequency performance. It can use a bulk capacitor response. While a unity-gain buffer (G = +1 V/V) is the (i.e., 1 µF or larger) within 100 mm to provide large, most sensitive to the capacitive loads, all gains show slow currents. This bulk capacitor can be shared with the same general behavior. other analog parts. When driving large capacitive loads with the
4.5 Unused Op Amps
MCP6421/2/4 op amps (e.g., > 60 pF when G = +1 V/V), a small series resistor at the output (RISO An unused op amp in a quad package (MCP6424) in Figure 4-5) improves the feedback loop’s phase mar- should be configured as shown in Figure 4-6. These gin (stability) by making the output load resistive at circuits prevent the output from toggling and causing higher frequencies. The bandwidth will be generally crosstalk. Circuit A sets the op amp at its minimum lower than the bandwidth with no capacitance load. noise gain. The resistor divider produces any desired reference voltage within the output voltage range of the op amp, and the op amp buffers that reference voltage. Circuit B uses the minimum number of components
–
RISO and operates as a comparator, but it may draw more
MCP642X
V current. OUT VIN
+
CL
¼ MCP6424 (A) ¼ MCP6424 (B)
VDD VDD
FIGURE 4-4:
Output Resistor, RISO Stabilizes Large Capacitive Loads. VDD R1 Figure 4-5 gives the recommended RISO values for the V different capacitive loads and gains. The x-axis is the R REF 2 normalized load capacitance (CL/GN), where GN is the circuit's noise gain. For non-inverting gains, GN and the Signal Gain are equal. For inverting gains, GN is R 1+|Signal Gain| (e.g., -1 V/V gives G 2 N = +2 V/V). V = V  ---------- REF DD R + R 1 2
FIGURE 4-6:
Unused Op Amps. DS20005165B-page 18  2013 Microchip Technology Inc. Document Outline Typical Application Package Types 1.0 Electrical Characteristics 1.1 Absolute Maximum Ratings † 1.2 Specifications TABLE 1-1: DC electrical specifications TABLE 1-2: AC Electrical Specifications TABLE 1-3: Temperature Specifications 1.3 Test Circuits FIGURE 1-1: AC and DC Test Circuit for Most Specifications. 2.0 Typical Performance Curves FIGURE 2-1: Input Offset Voltage. FIGURE 2-2: Input Offset Voltage Drift. FIGURE 2-3: Input Offset Voltage vs. Common Mode Input Voltage. FIGURE 2-4: Input Offset Voltage vs. Common Mode Input Voltage. FIGURE 2-5: Input Offset Voltage vs. Output Voltage. FIGURE 2-6: Input Offset Voltage vs. Power Supply Voltage. FIGURE 2-7: Input Noise Voltage Density vs. Common Mode Input Voltage. FIGURE 2-8: Input Noise Voltage Density vs. Frequency. FIGURE 2-9: CMRR, PSRR vs. Frequency. FIGURE 2-10: CMRR, PSRR vs. Ambient Temperature. FIGURE 2-11: Input Bias, Offset Current vs. Ambient Temperature. FIGURE 2-12: Input Bias Current vs. Common Mode Input Voltage. FIGURE 2-13: Quiescent Current vs. Ambient Temperature. FIGURE 2-14: Quiescent Current vs. Power Supply Voltage. FIGURE 2-15: Quiescent Current vs. Common Mode Input Voltage. FIGURE 2-16: Quiescent Current vs. Common Mode Input Voltage. FIGURE 2-17: Open-Loop Gain, Phase vs. Frequency. FIGURE 2-18: DC Open-Loop Gain vs. Ambient Temperature. FIGURE 2-19: DC Open-Loop Gain vs. Output Voltage Headroom. FIGURE 2-20: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature. FIGURE 2-21: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature. FIGURE 2-22: Output Short Circuit Current vs. Power Supply Voltage. FIGURE 2-23: Output Voltage Swing vs. Frequency. FIGURE 2-24: Output Voltage Headroom vs. Output Current. FIGURE 2-25: Output Voltage Headroom vs. Output Current. FIGURE 2-26: Output Voltage Headroom vs. Ambient Temperature. FIGURE 2-27: Output Voltage Headroom vs. Ambient Temperature. FIGURE 2-28: Slew Rate vs. Ambient Temperature. FIGURE 2-29: Small Signal Non-Inverting Pulse Response. FIGURE 2-30: Small Signal Inverting Pulse Response. FIGURE 2-31: Large Signal Non-Inverting Pulse Response. FIGURE 2-32: Large Signal Inverting Pulse Response. FIGURE 2-33: The MCP6421/2/4 Device Shows No Phase Reversal. FIGURE 2-34: Closed Loop Output Impedance vs. Frequency. FIGURE 2-35: Measured Input Current vs. Input Voltage (below VSS). FIGURE 2-36: EMIRR vs. Frequency. FIGURE 2-37: EMIRR vs. RF Input Peak- to-Peak Voltage. FIGURE 2-38: Channel-to-Channel Separation vs. Frequency. 3.0 Pin Descriptions TABLE 3-1: Pin Function Table 3.1 Analog Outputs 3.2 Analog Inputs 3.3 Power Supply Pins (VSS, VDD) 4.0 Application Information 4.1 Rail-to-Rail Input FIGURE 4-1: Simplified Analog Input ESD Structures. FIGURE 4-2: Protecting the Analog Inputs. FIGURE 4-3: Protecting the Analog Inputs. 4.2 Rail-to-Rail Output 4.3 Capacitive Loads FIGURE 4-4: Output Resistor, RISO Stabilizes Large Capacitive Loads. FIGURE 4-5: Recommended RISO Values for Capacitive Loads. 4.4 Supply Bypass 4.5 Unused Op Amps FIGURE 4-6: Unused Op Amps. 4.6 PCB Surface Leakage FIGURE 4-7: Example Guard Ring Layout for Inverting Gain. 4.7 Electromagnetic Interference Rejection Ratio (EMIRR) Definitions 4.8 Application Circuits FIGURE 4-8: CO Gas Sensor Circuit. FIGURE 4-9: Pressure Sensor Amplifier. FIGURE 4-10: Battery Current Sensing. 5.0 Design Aids 5.1 SPICE Macro Model 5.2 FilterLab® Software 5.3 Microchip Advanced Part Selector (MAPS) 5.4 Analog Demonstration and Evaluation Boards 5.5 Application Notes 6.0 Packaging Information 6.1 Package Marking Information Appendix A: Revision History Product Identification System Trademarks Worldwide Sales and Service