Datasheet AD7617 (Analog Devices) - 7

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AD7617 Data Sheet TIMING SPECIFICATIONS Universal Timing Specifications
VCC = 4.75 V to 5.25 V, VDRIVE = 2.3 V to 3.6 V, VREF = 2.5 V external reference/internal reference, TA = −40°C to +125°C, unless otherwise noted. Interface timing tested using a load capacitance (CLOAD) of 30 pF, dependent on VDRIVE and load capacitance for serial interface (see Table 15).
Table 2. Parameter1 Min Typ Max Unit Description
tCYCLE 1 µs Minimum time between consecutive CONVST rising edges (excluding burst and oversampling modes) tCONV_LOW 50 ns CONVST low pulse width tCONV_HIGH 50 ns CONVST high pulse width tBUSY_DELAY 32 ns CONVST high to BUSY high (manual mode) tCS_SETUP 20 ns BUSY fal ing edge to CS fal ing edge setup time tCH_SETUP 50 ns Channel select setup time in hardware mode for CHSELx tCH_HOLD 20 ns Channel select hold time in hardware mode for CHSELx tCONV 475 520 ns Conversion time for the selected channel pair tACQ 480 ns Acquisition time for the selected channel pair tQUIET 50 ns CS rising edge to next CONVST rising edge tRESET_LOW Partial Reset 40 500 ns Partial RESET low pulse width Full Reset 1.2 µs Full RESET low pulse width tDEVICE_SETUP Partial Reset 50 ns Time between partial RESET high and CONVST rising edge Full Reset 15 ms Time between full RESET high and CONVST rising edge tWRITE Partial Reset 50 ns Time between partial RESET high and CS for write operation Full Reset 240 µs Time between full RESET high and CS for write operation tRESET_WAIT 1 ms Time between stable VCC/VDRIVE and release of RESET (see Figure 51) tRESET_SETUP Time prior to release of RESET that queried hardware inputs must be stable for (see Figure 51) Partial Reset 10 ns Full Reset 0.05 ms tRESET_HOLD Time after release of RESET that queried hardware inputs must be stable for (see Figure 51) Partial Reset 10 ns Full Reset 0.24 ms 1 Not production tested. Sample tested during initial release to ensure compliance.
tCYCLE t t CONV_LOW CONV_HIGH t t BUSY_DELAY QUIET CONVST BUSY t t CONV ACQ tCS_SETUP CS t t CH_SETUP CH_HOLD HARDWARE
102
CHSEL0 TO CHx CHy MODE ONLY CHSEL2
16077- Figure 2. Universal Timing Diagram Across All Interfaces Rev. 0 | Page 6 of 51 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS Universal Timing Specifications Parallel Mode Timing Specifications Serial Mode Timing Specifications ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CONVERTER DETAILS ANALOG INPUT Analog Input Channel Selection Analog Input Ranges Analog Input Impedance Analog Input Clamp Protection Analog Input Antialiasing Filter ADC TRANSFER FUNCTION INTERNAL/EXTERNAL REFERENCE SHUTDOWN MODE DIGITAL FILTER APPLICATIONS INFORMATION FUNCTIONALITY OVERVIEW POWER SUPPLIES TYPICAL CONNECTIONS DEVICE CONFIGURATION OPERATIONAL MODE INTERNAL/EXTERNAL REFERENCE DIGITAL INTERFACE HARDWARE MODE SOFTWARE MODE RESET FUNCTIONALITY PIN FUNCTION OVERVIEW DIGITAL INTERFACE CHANNEL SELECTION Hardware Mode Software Mode PARALLEL INTERFACE Reading Conversion Results Writing Register Data Reading Register Data SERIAL INTERFACE Reading Conversion Results Writing Register Data Reading Register Data SEQUENCER HARDWARE MODE SEQUENCER SOFTWARE MODE SEQUENCER BURST SEQUENCER Hardware Mode Burst Software Mode Burst DIAGNOSTICS DIAGNOSTIC CHANNELS INTERFACE SELF TEST CRC REGISTER SUMMARY ADDRESSING REGISTERS CONFIGURATION REGISTER CHANNEL REGISTER INPUT RANGE REGISTERS Input Range Register A1 Input Range Register A2 Input Range Register B1 Input Range Register B2 SEQUENCER STACK REGISTERS STATUS REGISTER OUTLINE DIMENSIONS ORDERING GUIDE