Datasheet AD7605-4 (Analog Devices) - 7

link to page 9 link to page 8 link to page 9
AD7605-4 Data Sheet VINL = 0.1 × VDRIVE and VINL = 0.3 × VDRIVE and VINH = 0.9 × VDRIVE VINH = 0.7 × VDRIVE Logic Input Levels Logic Input Levels Parameter Min Typ Max Min Typ Max Unit Description
t15 6 6 ns Data hold time after RD falling edge t16 6 6 ns CS to DB15 to DB0 hold time t17 22 22 ns Delay from CS rising edge to DB15 to DB0 three- state enabled SERIAL READ OPERATION See Figure 6 fSCLK Frequency of serial read clock 23.5 20 MHz VDRIVE above 4.75 V 17 15 MHz VDRIVE above 3.3 V 14.5 12.5 MHz VDRIVE above 2.7 V 11.5 10 MHz VDRIVE above 2.3 V t18 Delay from CS until DOUTA/DOUTB three-state disabled/delay from CS until MSB valid 15 18 ns VDRIVE above 4.75 V 20 23 ns VDRIVE above 3.3 V 30 35 ns VDRIVE = 2.3 V to 2.7 V t19 Data access time after SCLK rising edge 17 20 ns VDRIVE above 4.75 V 23 26 ns VDRIVE above 3.3 V 27 32 ns VDRIVE above 2.7 V 34 39 ns VDRIVE above 2.3 V t20 0.4 × tSCLK 0.4 × tSCLK ns SCLK low pulse width t21 0.4 × tSCLK 0.4 × tSCLK ns SCLK high pulse width t22 7 7 ns SCLK rising edge to DOUTA/DOUTB valid hold time t23 22 22 ns CS rising edge to DOUTA/DOUTB three-state enabled FRSTDATA OPERATION See Figure 4 and Figure 7 t24 Delay from CS falling edge until FRSTDATA three- state disabled 15 18 ns VDRIVE above 4.75 V 20 23 ns VDRIVE above 3.3 V 25 30 ns VDRIVE above 2.7 V 30 35 ns VDRIVE above 2.3 V t25 Delay from CS falling edge until FRSTDATA high, serial mode 15 18 ns VDRIVE above 4.75 V 20 23 ns VDRIVE above 3.3 V 25 30 ns VDRIVE above 2.7 V 30 35 ns VDRIVE above 2.3 V t26 Delay from RD falling edge to FRSTDATA high 16 19 ns VDRIVE above 4.75 V 20 23 ns VDRIVE above 3.3 V 25 30 ns VDRIVE above 2.7 V 30 35 ns VDRIVE above 2.3 V t27 Delay from RD falling edge to FRSTDATA low 19 22 ns VDRIVE = 3.3 V to 5.25V 24 29 ns VDRIVE = 2.3 V to 2.7V t28 Delay from 16th SCLK falling edge to FRSTDATA low 17 20 ns VDRIVE = 3.3 V to 5.25V 22 27 ns VDRIVE = 2.3 V to 2.7V t29 24 29 ns CS rising edge until FRSTDATA three-state enabled Rev. 0 | Page 6 of 27 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CONVERTER DETAILS ANALOG INPUT Analog Input Ranges Analog Input Impedance Analog Input Clamp Protection Analog Input Antialiasing Filter Track-and-Hold Amplifiers ADC TRANSFER FUNCTION INTERNAL/EXTERNAL REFERENCE TYPICAL CONNECTION DIAGRAM POWER-DOWN MODES CONVERSION CONTROL Simultaneous Sampling on All Analog Input Channels Simultaneously Sampling Two Sets of Channels APPLICATIONS INFORMATION PARALLEL INTERFACE (/SER/BYTE SEL = 0) PARALLEL BYTE (/SER/BYTE SEL = 1, DB15/BYTE SEL = 1) SERIAL INTERFACE (/SER/BYTE SEL = 1) READING DURING CONVERSION LAYOUT GUIDELINES OUTLINE DIMENSIONS ORDERING GUIDE