Datasheet LTC1860L, LTC1861L (Analog Devices) - 7
| 制造商 | Analog Devices |
| 描述 | µPower, 3V, 12-Bit, 150ksps 1- and 2-Channel ADCs in MSOP |
| 页数 / 页 | 12 / 7 — PI FU CTIO S. LTC1861L (MSOP Package). LTC1861L (SO-8 Package). CONV (Pin … |
| 文件格式/大小 | PDF / 240 Kb |
| 文件语言 | 英语 |
PI FU CTIO S. LTC1861L (MSOP Package). LTC1861L (SO-8 Package). CONV (Pin 1):. CH0, CH1 (Pins 2, 3):. AGND (Pin 4):. GND (Pin 4):
该数据表的模型线
文件文字版本
LTC1860L/LTC1861L
U U U PI FU CTIO S LTC1861L (MSOP Package) LTC1861L (SO-8 Package) CONV (Pin 1):
Convert Input. A logic high on this input
CONV (Pin 1):
Convert Input. A logic high on this input starts the A/D conversion process. If the CONV input is left starts the A/D conversion process. If the CONV input is left high after the A/D conversion is finished, the part powers high after the A/D conversion is finished, the part powers down. A logic low on this input enables the SDO pin, down. A logic low on this input enables the SDO pin, allowing the data to be shifted out. allowing the data to be shifted out.
CH0, CH1 (Pins 2, 3):
Analog Inputs. These inputs must
CH0, CH1 (Pins 2, 3):
Analog Inputs. These inputs must be free of noise with respect to AGND. be free of noise with respect to GND.
AGND (Pin 4):
Analog Ground. AGND should be tied
GND (Pin 4):
Analog Ground. GND should be tied directly directly to an analog ground plane. to an analog ground plane.
DGND (Pin 5):
Digital Ground. DGND should be tied
SDI (Pin 5):
Digital Data Input. The A/D configuration directly to an analog ground plane. word is shifted into this input.
SDI (Pin 6):
Digital Data Input. The A/D configuration
SDO (Pin 6):
Digital Data Output. The A/D conversion word is shifted into this input. result is shifted out of this output.
SDO (Pin 7):
Digital Data Output. The A/D conversion
SCK (Pin 7):
Shift Clock Input. This clock synchronizes the result is shifted out of this output. serial data transfer.
SCK (Pin 8):
Shift Clock Input. This clock synchronizes the
VCC (Pin 8):
Positive Supply. This supply must be kept serial data transfer. free of noise and ripple by bypassing directly to the analog ground plane. VREF is tied internally to this pin.
VCC (Pin 9):
Positive Supply. This supply must be kept free of noise and ripple by bypassing directly to the analog ground plane.
VREF (Pin 10):
Reference Input. The reference input de- fines the span of the A/D converter and must be kept free of noise with respect to AGND.
U U W FUNCTIONAL BLOCK DIAGRA
VCC CONV (SDI) SCK CONVERT BIAS AND SERIAL SDO CLK SHUTDOWN PORT DATA IN 12-BITS IN+ + (CH0) 12-BIT SAMPLING DATA OUT ADC IN– – (CH1) PIN NAMES IN PARENTHESES REFER TO LTC1861L 1860L/61L BD GND VREF 18601Lf 7
U U U PI FU CTIO S LTC1861L (MSOP Package) LTC1861L (SO-8 Package) CONV (Pin 1):
Convert Input. A logic high on this input
CONV (Pin 1):
Convert Input. A logic high on this input starts the A/D conversion process. If the CONV input is left starts the A/D conversion process. If the CONV input is left high after the A/D conversion is finished, the part powers high after the A/D conversion is finished, the part powers down. A logic low on this input enables the SDO pin, down. A logic low on this input enables the SDO pin, allowing the data to be shifted out. allowing the data to be shifted out.
CH0, CH1 (Pins 2, 3):
Analog Inputs. These inputs must
CH0, CH1 (Pins 2, 3):
Analog Inputs. These inputs must be free of noise with respect to AGND. be free of noise with respect to GND.
AGND (Pin 4):
Analog Ground. AGND should be tied
GND (Pin 4):
Analog Ground. GND should be tied directly directly to an analog ground plane. to an analog ground plane.
DGND (Pin 5):
Digital Ground. DGND should be tied
SDI (Pin 5):
Digital Data Input. The A/D configuration directly to an analog ground plane. word is shifted into this input.
SDI (Pin 6):
Digital Data Input. The A/D configuration
SDO (Pin 6):
Digital Data Output. The A/D conversion word is shifted into this input. result is shifted out of this output.
SDO (Pin 7):
Digital Data Output. The A/D conversion
SCK (Pin 7):
Shift Clock Input. This clock synchronizes the result is shifted out of this output. serial data transfer.
SCK (Pin 8):
Shift Clock Input. This clock synchronizes the
VCC (Pin 8):
Positive Supply. This supply must be kept serial data transfer. free of noise and ripple by bypassing directly to the analog ground plane. VREF is tied internally to this pin.
VCC (Pin 9):
Positive Supply. This supply must be kept free of noise and ripple by bypassing directly to the analog ground plane.
VREF (Pin 10):
Reference Input. The reference input de- fines the span of the A/D converter and must be kept free of noise with respect to AGND.
U U W FUNCTIONAL BLOCK DIAGRA
VCC CONV (SDI) SCK CONVERT BIAS AND SERIAL SDO CLK SHUTDOWN PORT DATA IN 12-BITS IN+ + (CH0) 12-BIT SAMPLING DATA OUT ADC IN– – (CH1) PIN NAMES IN PARENTHESES REFER TO LTC1861L 1860L/61L BD GND VREF 18601Lf 7