Datasheet AD9637 (Analog Devices) - 4

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Data Sheet AD9637 SPECIFICATIONS DC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted.
Table 1. AD9637-40 AD9637-80 Parameter
1
Temp Min Typ Max Min Typ Max Unit
RESOLUTION 12 12 Bits ACCURACY No Missing Codes Full Guaranteed Guaranteed Offset Error Full −0.6 −0.3 +0.1 −0.7 −0.3 +0.1 % FSR Offset Matching Full 0.0 0.2 0.6 0.0 0.2 0.6 % FSR Gain Error Full −8.0 −2.1 +2.0 −7.0 −3.2 +1.0 % FSR Gain Matching Full −1.0 +1.7 +5.0 −1.0 +2.3 +6.0 % FSR Differential Nonlinearity (DNL) Full −0.8 ±0.3 +0.8 −0.8 ±0.4 +0.8 LSB Integral Nonlinearity (INL) Full −1.0 ±0.4 +1.0 −1.2 ±0.5 +1.2 LSB TEMPERATURE DRIFT Offset Error Full ±2 ±2 ppm/°C INTERNAL VOLTAGE REFERENCE Output Voltage (1 V Mode) Full 0.98 0.99 1.01 0.98 0.99 1.01 V Load Regulation at 1.0 mA (VREF = 1 V) Full 2 2 mV Input Resistance Full 7.5 7.5 kΩ INPUT REFERRED NOISE VREF = 1.0 V 25° C 0. 36 0. 49 LSB rms ANALOG INPUTS Differential Input Voltage (VREF = 1 V) Full 2 2 V p-p Common-Mode Voltage Full 0.9 0.9 V Common-Mode Range Full 0.5 1.3 0.5 1.3 V Differential Input Resistance 5.2 5.2 kΩ Differential Input Capacitance Full 3.5 3.5 pF POWER SUPPLY AVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 V DRVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 V IAVDD (Eight Channels) Full 142 151 221 234 mA IDRVDD (Eight Channels, ANSI-644 Mode) Full 51 79 58 85 mA IDRVDD (Eight Channels, Reduced Range Mode) 25°C 36 43 mA TOTAL POWER CONSUMPTION Total Power Dissipation (Eight Channels, ANSI-644 Mode) Full 347 414 502 574 mW Total Power Dissipation (Eight Channels, Reduced Range Mode) 25°C 320 475 mW Power-Down Dissipation 25°C 1 1 mW Standby Dissipation2 25°C 72 98 mW 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed. 2 Can be controlled via the SPI. Rev. A | Page 3 of 40 Document Outline Features Applications General Description Functional Block Diagram Product Highlights Revision History Specifications DC Specifications AC Specifications Digital Specifications Switching Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings Thermal Characteristics ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics AD9637-80 AD9637-40 Equivalent Circuits Theory of Operation Analog Input Considerations Input Common Mode Differential Input Configurations Voltage Reference Internal Reference Connection External Reference Operation Clock Input Considerations Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations Power Dissipation and Power-Down Mode Digital Outputs and Timing SDIO/DFS Pin SCLK/DTP Pin CSB Pin RBIAS Pin Built-In Output Test Modes Output Test Modes Serial Port Interface (SPI) Configuration Using the SPI Hardware Interface Configuration Without the SPI SPI Accessible Features Memory Map Reading the Memory Map Register Table Open Locations Default Values Logic Levels Channel-Specific Registers Memory Map Register Table Memory Map Register Descriptions Device Index (Register 0x04 and Register 0x05) Transfer (Register 0xFF) Power Modes (Register 0x08) Bits[7:6]—Open Bits[1:0]—Internal Power-Down Mode Enhancement Control (Register 0x0C) Bits[7:3]—Open Bit 2—Chop Mode Bits[1:0]—Open Output Mode (Register 0x14) Bit 7—Open Bit 6—LVDS-ANSI/LVDS-IEEE Option Bits[5:3]—Open Bit 2—Output Invert Bit 1—Open Bit 0—Output Format Output Adjust (Register 0x15) Bits[7:6]—Open Bits[5:4]—Output Driver Termination Bits[3:1]—Open Bit 0—Output Drive Output Phase (Register 0x16) Bit 7—Open Bits[6:4]—Input Clock Phase Adjust Bits[3:0]—Output Clock Phase Adjust Resolution/Sample Rate Override (Register 0x100) User I/O Control 2 (Register 0x101) Bits[7:1]—Open Bit 0—SDIO Pull-Down User I/O Control 3 (Register 0x102) Bits[7:4]—Open Bit 3—VCM Power-Down Bits[2:0]—Open Applications Information Design Guidelines Power and Ground Recommendations Clock Stability Considerations Exposed Pad Thermal Heat Slug Recommendations VCM Reference Decoupling SPI Port Outline Dimensions Ordering Guide