Datasheet AD9637 (Analog Devices) - 3
| 制造商 | Analog Devices |
| 描述 | Octal, 12-Bit, 40/80 MSPS Serial LVDS 1.8 V A/D Converter |
| 页数 / 页 | 41 / 3 — AD9637. Data Sheet. TABLE OF CONTENTS. REVISION HISTORY. 4/13—Rev. 0 to … |
| 修订版 | A |
| 文件格式/大小 | PDF / 1.0 Mb |
| 文件语言 | 英语 |
AD9637. Data Sheet. TABLE OF CONTENTS. REVISION HISTORY. 4/13—Rev. 0 to Rev. A. 10/11—Revision 0: Initial Version
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AD9637 Data Sheet TABLE OF CONTENTS
Features .. 1 Power Dissipation and Power-Down Mode ... 22 Applications ... 1 Digital Outputs and Timing ... 23 General Description ... 1 Built-In Output Test Modes .. 27 Functional Block Diagram .. 1 Output Test Modes ... 27 Product Highlights ... 1 Serial Port Interface (SPI) .. 28 Revision History ... 2 Configuration Using the SPI ... 28 Specifications ... 3 Hardware Interface ... 29 DC Specifications ... 3 Configuration Without the SPI .. 29 AC Specifications .. 4 SPI Accessible Features .. 29 Digital Specifications ... 5 Memory Map .. 30 Switching Specifications .. 6 Reading the Memory Map Register Table ... 30 Timing Specifications .. 6 Memory Map Register Table ... 31 Absolute Maximum Ratings .. 8 Memory Map Register Descriptions .. 34 Thermal Characteristics .. 8 Applications Information .. 36 ESD Caution .. 8 Design Guidelines .. 36 Pin Configuration and Function Descriptions ... 9 Power and Ground Recommendations ... 36 Typical Performance Characteristics ... 11 Clock Stability Considerations ... 36 AD9637-80 .. 11 Exposed Pad Thermal Heat Slug Recommendations .. 36 AD9637-40 .. 14 VCM ... 36 Equivalent Circuits ... 17 Reference Decoupling .. 36 Theory of Operation .. 18 SPI Port .. 36 Analog Input Considerations .. 18 Outline Dimensions ... 37 Voltage Reference ... 19 Ordering Guide .. 37 Clock Input Considerations .. 20
REVISION HISTORY 4/13—Rev. 0 to Rev. A
Added Common-Mode Range ... 3 Changes to AC Specifications Section ... 4 Added Propagation Delay of 1.5 ns Min and 3.1 ns Max; Table 4 .. 6 Added CLK Divider = 8 to Figure 7, Figure 9, Figure 10, and Figure 11 Captions .. 11 Added CLK Divider = 8 to Figure 22, Figure 24, and Figure 25 Captions ... 14 Changes to Figure 36 and Figure 37 ... 17 Changes to Figure 44 .. 18 Changes to Figure 56 .. 22 Changes to Digital Outputs and Timing Section ... 23 Changes to Channel Specific Registers Section .. 30 Changes to Register 0x21, Bit 3; Table 17 .. 33 Changes to Bits[6:4]—Input Clock Phase Adjust Section... 35 Added Clock Stability Considerations Section ... 36 Updated Outline Dimensions ... 37
10/11—Revision 0: Initial Version
Rev. A | Page 2 of 40 Document Outline Features Applications General Description Functional Block Diagram Product Highlights Revision History Specifications DC Specifications AC Specifications Digital Specifications Switching Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings Thermal Characteristics ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics AD9637-80 AD9637-40 Equivalent Circuits Theory of Operation Analog Input Considerations Input Common Mode Differential Input Configurations Voltage Reference Internal Reference Connection External Reference Operation Clock Input Considerations Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations Power Dissipation and Power-Down Mode Digital Outputs and Timing SDIO/DFS Pin SCLK/DTP Pin CSB Pin RBIAS Pin Built-In Output Test Modes Output Test Modes Serial Port Interface (SPI) Configuration Using the SPI Hardware Interface Configuration Without the SPI SPI Accessible Features Memory Map Reading the Memory Map Register Table Open Locations Default Values Logic Levels Channel-Specific Registers Memory Map Register Table Memory Map Register Descriptions Device Index (Register 0x04 and Register 0x05) Transfer (Register 0xFF) Power Modes (Register 0x08) Bits[7:6]—Open Bits[1:0]—Internal Power-Down Mode Enhancement Control (Register 0x0C) Bits[7:3]—Open Bit 2—Chop Mode Bits[1:0]—Open Output Mode (Register 0x14) Bit 7—Open Bit 6—LVDS-ANSI/LVDS-IEEE Option Bits[5:3]—Open Bit 2—Output Invert Bit 1—Open Bit 0—Output Format Output Adjust (Register 0x15) Bits[7:6]—Open Bits[5:4]—Output Driver Termination Bits[3:1]—Open Bit 0—Output Drive Output Phase (Register 0x16) Bit 7—Open Bits[6:4]—Input Clock Phase Adjust Bits[3:0]—Output Clock Phase Adjust Resolution/Sample Rate Override (Register 0x100) User I/O Control 2 (Register 0x101) Bits[7:1]—Open Bit 0—SDIO Pull-Down User I/O Control 3 (Register 0x102) Bits[7:4]—Open Bit 3—VCM Power-Down Bits[2:0]—Open Applications Information Design Guidelines Power and Ground Recommendations Clock Stability Considerations Exposed Pad Thermal Heat Slug Recommendations VCM Reference Decoupling SPI Port Outline Dimensions Ordering Guide
AD9637 Data Sheet TABLE OF CONTENTS
Features .. 1 Power Dissipation and Power-Down Mode ... 22 Applications ... 1 Digital Outputs and Timing ... 23 General Description ... 1 Built-In Output Test Modes .. 27 Functional Block Diagram .. 1 Output Test Modes ... 27 Product Highlights ... 1 Serial Port Interface (SPI) .. 28 Revision History ... 2 Configuration Using the SPI ... 28 Specifications ... 3 Hardware Interface ... 29 DC Specifications ... 3 Configuration Without the SPI .. 29 AC Specifications .. 4 SPI Accessible Features .. 29 Digital Specifications ... 5 Memory Map .. 30 Switching Specifications .. 6 Reading the Memory Map Register Table ... 30 Timing Specifications .. 6 Memory Map Register Table ... 31 Absolute Maximum Ratings .. 8 Memory Map Register Descriptions .. 34 Thermal Characteristics .. 8 Applications Information .. 36 ESD Caution .. 8 Design Guidelines .. 36 Pin Configuration and Function Descriptions ... 9 Power and Ground Recommendations ... 36 Typical Performance Characteristics ... 11 Clock Stability Considerations ... 36 AD9637-80 .. 11 Exposed Pad Thermal Heat Slug Recommendations .. 36 AD9637-40 .. 14 VCM ... 36 Equivalent Circuits ... 17 Reference Decoupling .. 36 Theory of Operation .. 18 SPI Port .. 36 Analog Input Considerations .. 18 Outline Dimensions ... 37 Voltage Reference ... 19 Ordering Guide .. 37 Clock Input Considerations .. 20
REVISION HISTORY 4/13—Rev. 0 to Rev. A
Added Common-Mode Range ... 3 Changes to AC Specifications Section ... 4 Added Propagation Delay of 1.5 ns Min and 3.1 ns Max; Table 4 .. 6 Added CLK Divider = 8 to Figure 7, Figure 9, Figure 10, and Figure 11 Captions .. 11 Added CLK Divider = 8 to Figure 22, Figure 24, and Figure 25 Captions ... 14 Changes to Figure 36 and Figure 37 ... 17 Changes to Figure 44 .. 18 Changes to Figure 56 .. 22 Changes to Digital Outputs and Timing Section ... 23 Changes to Channel Specific Registers Section .. 30 Changes to Register 0x21, Bit 3; Table 17 .. 33 Changes to Bits[6:4]—Input Clock Phase Adjust Section... 35 Added Clock Stability Considerations Section ... 36 Updated Outline Dimensions ... 37
10/11—Revision 0: Initial Version
Rev. A | Page 2 of 40 Document Outline Features Applications General Description Functional Block Diagram Product Highlights Revision History Specifications DC Specifications AC Specifications Digital Specifications Switching Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings Thermal Characteristics ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics AD9637-80 AD9637-40 Equivalent Circuits Theory of Operation Analog Input Considerations Input Common Mode Differential Input Configurations Voltage Reference Internal Reference Connection External Reference Operation Clock Input Considerations Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations Power Dissipation and Power-Down Mode Digital Outputs and Timing SDIO/DFS Pin SCLK/DTP Pin CSB Pin RBIAS Pin Built-In Output Test Modes Output Test Modes Serial Port Interface (SPI) Configuration Using the SPI Hardware Interface Configuration Without the SPI SPI Accessible Features Memory Map Reading the Memory Map Register Table Open Locations Default Values Logic Levels Channel-Specific Registers Memory Map Register Table Memory Map Register Descriptions Device Index (Register 0x04 and Register 0x05) Transfer (Register 0xFF) Power Modes (Register 0x08) Bits[7:6]—Open Bits[1:0]—Internal Power-Down Mode Enhancement Control (Register 0x0C) Bits[7:3]—Open Bit 2—Chop Mode Bits[1:0]—Open Output Mode (Register 0x14) Bit 7—Open Bit 6—LVDS-ANSI/LVDS-IEEE Option Bits[5:3]—Open Bit 2—Output Invert Bit 1—Open Bit 0—Output Format Output Adjust (Register 0x15) Bits[7:6]—Open Bits[5:4]—Output Driver Termination Bits[3:1]—Open Bit 0—Output Drive Output Phase (Register 0x16) Bit 7—Open Bits[6:4]—Input Clock Phase Adjust Bits[3:0]—Output Clock Phase Adjust Resolution/Sample Rate Override (Register 0x100) User I/O Control 2 (Register 0x101) Bits[7:1]—Open Bit 0—SDIO Pull-Down User I/O Control 3 (Register 0x102) Bits[7:4]—Open Bit 3—VCM Power-Down Bits[2:0]—Open Applications Information Design Guidelines Power and Ground Recommendations Clock Stability Considerations Exposed Pad Thermal Heat Slug Recommendations VCM Reference Decoupling SPI Port Outline Dimensions Ordering Guide