Datasheet AD9239 (Analog Devices) - 6

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Data Sheet AD9239 DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, 1.25 V p-p differential input, AIN = −1.0 dBFS, DCS enabled, unless otherwise noted.
Table 3. AD9239BCPZ-170 AD9239BCPZ-210 AD9239BCPZ-250 Parameter1 Temp Min Typ Max Min Typ Max Min Typ Max Unit
CLOCK INPUTS (CLK+, CLK–) Logic Compliance Full LVPECL/LVDS/CMOS LVPECL/LVDS/CMOS LVPECL/LVDS/CMOS Differential Input Voltage Full 0.2 6 0.2 6 0.2 6 V p-p Input Voltage Range Full AVDD − AVDD + AVDD − AVDD + AVDD − AVDD + V 0.3 1.6 0.3 1.6 0.3 1.6 Internal Common-Mode Bias Full 1.2 1.2 1.2 V Input Common-Mode Voltage Full 1.1 AVDD 1.1 AVDD 1.1 AVDD V High Level Input Voltage (VIH) Full 1.2 3.6 1.2 3.6 1.2 3.6 V Low Level Input Voltage (VIL) Full 0 0.8 0 0.8 0 0.8 V High Level Input Current (IIH) Full −10 +10 −10 +10 −10 +10 µA Low Level Input Current (IIL) Full −10 +10 −10 +10 −10 +10 µA Differential Input Resistance 25°C 16 20 24 16 20 24 16 20 24 kΩ Input Capacitance 25°C 4 4 4 pF LOGIC INPUTS (PDWN, CSB, SDI/ SDIO, SCLK, RESET, PGMx)2 Logic 1 Voltage Full 0.8 × 0.8 × 0.8 × V AVDD AVDD AVDD Logic 0 Voltage Full 0.2 × 0.2 × 0.2 × V AVDD AVDD AVDD Logic 1 Input Current (CSB) Full 0 0 0 µA Logic 0 Input Current (CSB) Full −60 −60 −60 µA Logic 1 Input Current Full 55 55 55 µA (SCLK, PDWN, SDI/SDIO, RESET, PGMx) Logic 0 Input Current Full 0 0 0 µA (SCLK, PDWN, SDI/SDIO, RESET, PGMx) Input Resistance 25°C 30 30 30 kΩ Input Capacitance 25°C 4 4 4 pF LOGIC OUTPUTS (SDO) Logic 1 Voltage Full 1.2 AVDD + 1.2 AVDD + 1.2 AVDD + V 0.3 0.3 0.3 Logic 0 Voltage Full 0 0.3 0 0.3 0 0.3 V DIGITAL OUTPUTS (DOUT + x, DOUT − x) Logic Compliance Current Current Current mode mode mode logic logic logic Differential Output Voltage Full 0.8 0.8 0.8 V Common-Mode Level Full DRVDD/2 DRVDD/2 DRVDD/2 V 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and details on how these tests were completed. 2 Specified for 13 SDI/SDIO pins sharing the same connection. Rev. E | Page 5 of 40 Document Outline Features Applications Functional Block Diagram General Description Product Highlights Table of Contents Revision History Specifications AC Specifications Digital Specifications Switching Specifications Timing Diagram Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Description Typical Performance Characteristics Equivalent Circuits Theory of Operation Analog Input Considerations Differential Input Configurations Single-Ended Input Configuration Clock Input Considerations Clock Duty Cycle Considerations Clock Jitter Considerations Power Dissipation Digital Start-Up Sequence Minimize Skew and Time Misalignment (Optional) Link Initialization (Required) Digital Outputs and Timing Digital Output Scrambler and Error Code Correction Error Correction Code Scramblers Inverter Balance Example Calculating the Parity Bits for the Hamming Code TEMPOUT Pin RBIAS Pin VCMx Pins RESET Pin PDWN Pin SDO Pin SDI/SDIO Pin SCLK Pin CSB Pin PGMx Pins Serial Port Interface (SPI) Hardware Interface Memory Map Reading the Memory Map Table Reserved Locations Default Values Logic Levels Power and Ground Recommendations Exposed Paddle Thermal Heat Slug Recommendations Outline Dimensions Ordering Guide