Datasheet AD7762 (Analog Devices) - 8

Data Sheet AD7762 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS E V ND ND ND 1 1 DRI DG V DG DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DG DB8 DB9 DB10 DB 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 DGND 1 48 DB12 MCLKGND PIN 1 2 47 DB13 MCLK 3 46 DB14 AV 4 45 DB15 DD2 AGND2 5 44 VDRIVE AV 6 43 DGND DD1 AGND1 7 42 DGND DECAPA 8 AD7762 41 DVDD REFGND 9 TOP VIEW 40 CS (Not to Scale) V 10 39 RD/WR REF+ AGND4 11 38 DRDY AV 12 37 RESET DD4 AGND2 13 36 SYNC AV 14 35 DGND DD2 AV 15 34 AGND1 DD2 AGND2 16 33 AVDD1 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 + – B AS A+ A– A– A+ IN IN BI ND2 DD3 DD2 IN IN ND3 V V ND2 ND3 ND3 ND3 R V V UT UT V V CAP AG O O A A V V AG AG AG AG AG DE
005
NOTES 1. CONNECT THE EXPOSED PAD TO AGNDx WITH SIX TO EIGHT VIAS.
05477- Figure 4. 64-Lead TQFP Pin Configuration
Table 5. Pin Function Descriptions Pin No. Mnemonic Description
6, 33 AVDD1 2.5 V Power Supply for Modulator. These pins should be decoupled to AGND1 with 100 nF and 10 µF capacitors on each pin. 4, 14, 15, 27 AVDD2 5 V Power Supply. These pins should be decoupled to AGND2 with 100 nF capacitors on each of Pin 4, Pin 14, and Pin 15. Pin 27 should be connected to Pin 14 via a 15 nH inductor. 24 AVDD3 3.3 V to 5 V Power Supply for Differential Amplifier. These pins should be decoupled to AGND3 with a 100 nF capacitor. 12 AVDD4 3.3 V to 5 V Power Supply for Reference Buffer. This pin should be decoupled to AGND4 with a 10 nF capacitor in series with a 10 Ω resistor. 7, 34 AGND1 Power Supply Ground for Analog Circuitry Powered by AVDD1. 5, 13, 16, 18, 28 AGND2 Power Supply Ground for Analog Circuitry Powered by AVDD2. 23, 29, 31, 32 AGND3 Power Supply Ground for Analog Circuitry Powered by AVDD3. 11 AGND4 Power Supply Ground for Analog Circuitry Powered by AVDD4. 9 REFGND Reference Ground. Ground connection for the reference voltage. 41 DVDD 2.5 V Power Supply for Digital Circuitry and FIR Filter. This pin should be decoupled to DGND with a 100 nF capacitor. 44, 63 VDRIVE Logic Power Supply Input, 1.8 V to 2.5 V. The voltage supplied at these pins determines the operating voltage of the logic interface. Both these pins must be connected together and tied to the same supply. Each pin should also be decoupled to DGND with a100 nF capacitor. 1, 35, 42, 43, DGND Ground Reference for Digital Circuitry. 53, 62, 64 19 VINA+ Positive Input to Differential Amplifier. 20 VINA− Negative Input to Differential Amplifier. 21 VOUTA− Negative Output from Differential Amplifier. 22 VOUTA+ Positive Output from Differential Amplifier. 25 VIN+ Positive Input to the Modulator. 26 VIN− Negative Input to the Modulator. Rev. A | Page 7 of 28 Document Outline Features Applications Functional Block Diagram General Description Table of Contents Revision History Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Terminology Typical Performance Characteristics Theory of Operation AD7762 Interface Reading Data Sharing the Parallel Bus Writing to the AD7762 Reading Status and Other Registers Clocking the AD7762 Example 1 Example 2 Driving the AD7762 Using the AD7762 Bias Resistor Selection Decoupling and Layout Recommendations Supply Decoupling Additional Decoupling Reference Voltage Filtering Differential Amplifier Components Layout Considerations Programmable FIR Filter Downloading a User-Defined Filter Example Filter Download AD7762 Registers Control Register 1—Reg 0x0001 Default Value 0x001A Control Register 2—Address 0x0002 Default Value 0x009B Status Register (Read Only) Offset Register—Address 0x0003 Non-bitmapped, Default Value 0x0000 Gain Register—Address 0x0004 Non-bitmapped, Default Value 0xA000 Overrange Register—Address 0x0005 Non-bitmapped, Default Value 0xCCCC Outline Dimensions Ordering Guide