link to page 3 link to page 6 AD7912/AD7922ParameterA Grade1UnitTest Conditions/Comments CONVERSION RATE Conversion Time 777 ns max 14 SCLK cycles with SCLK at 18 MHz Track-and-Hold Acquisition Time2 290 ns max Throughput Rate 1 MSPS max POWER REQUIREMENTS VDD 2.35/5.25 V min/max IDD Digital I/Ps = 0 V or VDD Normal Mode (Static) 3 mA typ VDD = 4.75 V to 5.25 V, SCLK on or off 1.5 mA typ VDD = 2.35 V to 3.6 V, SCLK on or off Normal Mode (Operational) 4 mA max VDD = 4.75 V to 5.25 V, fSAMPLE = 1 MSPS 2 mA max VDD = 2.35 V to 3.6 V, fSAMPLE = 1 MSPS Full Power-Down Mode (Static) 1 µA max SCLK on or off, typically 50 nA Full Power-Down Mode (Dynamic) 0.48 mA typ VDD = 5 V, fSCLK = 18 MHz, fSAMPLE = 100 kSPS 0.26 mA typ VDD = 3 V, fSCLK = 18 MHz, fSAMPLE = 100 kSPS Power Dissipation4 Normal Mode (Operational) 20 mW max VDD = 5 V, fSAMPLE = 1 MSPS 6 mW max VDD = 3 V, fSAMPLE = 1 MSPS Full Power-Down 5 µW max VDD = 5 V 1 Operational from VDD = 2 V, with VIH = 1.9 V minimum and VIL = 0.1 V maximum. 2 See the Terminology section. 3 Guaranteed by characterization. 4 See the Power vs. Throughput Rate section. Rev. 0 | Page 4 of 32 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS SPECIFICATIONS AD7912 SPECIFICATIONS AD7922 SPECIFICATIONS TIMING SPECIFICATIONS TIMING DIAGRAMS TIMING EXAMPLES Timing Example 1 Timing Example 2 ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TERMINOLOGY TYPICAL PERFORMANCE CHARACTERISTICS CIRCUIT INFORMATION CONVERTER OPERATION ADC TRANSFER FUNCTION TYPICAL CONNECTION DIAGRAM ANALOG INPUT DIGITAL INPUTS DIN INPUT DOUT OUTPUT MODES OF OPERATION NORMAL MODE POWER-DOWN MODE POWER-UP TIME DAISY-CHAIN MODE DAISY-CHAIN EXAMPLE POWER VS. THROUGHPUT RATE SERIAL INTERFACE MICROPROCESSOR INTERFACING AD7912/AD7922 to TMS320C541 Interface AD7912/AD7922 to ADSP-218x AD7912/AD7922 to DSP563xx Interface APPLICATION HINTS GROUNDING AND LAYOUT EVALUATING AD7912/AD7922 PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE