Datasheet AD7732 (Analog Devices) - 3
| 制造商 | Analog Devices |
| 描述 | 2-Channel, ±10 V Input Range, High Throughput, 24-Bit Sigma-Delta ADC |
| 页数 / 页 | 33 / 3 — AD7732. TABLE OF CONTENTS. REVISION HISTORY 6/11—Rev. 0 to Rev. A. … |
| 修订版 | A |
| 文件格式/大小 | PDF / 439 Kb |
| 文件语言 | 英语 |
AD7732. TABLE OF CONTENTS. REVISION HISTORY 6/11—Rev. 0 to Rev. A. 2/03—Revision 0: Initial Version
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AD7732 TABLE OF CONTENTS
AD7732—Specifications.. 3 Digital Interface Description .. 22 Timing Specifications... 6 Hardware ... 22 Absolute Maximum Ratings.. 8 Reset ... 23 Typical Performance Characteristics ... 9 Access the AD7732 Registers.. 23 Output Noise and Resolution Specification.. 10 Single Conversion and Reading Data .. 23 Chopping Enabled.. 10 Dump Mode.. 24 Chopping Disabled... 11 Continuous Conversion Mode ... 24 Pin Configurations and Functional Descriptions .. 12 Continuous Read (Continuous Conversion) Mode .. 25 Register Description... 14 Circuit Description... 26 Register Access.. 15 Analog Front End... 26 Communications Register... 15 Analog Input’s Extended Voltage Range ... 27 I/O Port Register... 16 Chopping ... 27 Revision Register .. 16 Multiplexer, Conversion, and Data Output Timing ... 28 Test Register .. 16 Sigma-Delta ADC .. 28 ADC Status Register... 17 Frequency Response .. 28 Checksum Register... 17 Voltage Reference Inputs... 29 ADC Zero-Scale Calibration Register ... 17 Reference Detect... 29 ADC Full-Scale Register.. 17 I/O Port.. 30 Channel Data Registers.. 17 Calibration... 30 Channel Zero-Scale Calibration Registers .. 18 ADC Zero-Scale Self-Calibration .. 30 Channel Full-Scale Calibration Registers.. 18 Per Channel System Calibration .. 30 Channel Status Registers ... 18 High Common-Mode Voltage Application .. 31 Channel Setup Registers .. 19 Outline Dimensions ... 32 Channel Conversion Time Registers ... 19 Ordering Guide .. 32 Mode Register ... 20
REVISION HISTORY 6/11—Rev. 0 to Rev. A
Changes to Figure 22.. 25 Changes to ADC Performance Chopping Enabled, Offset Error Changes to Ordering Guide .. 32 (Unipolar, Bipolar) Parameter, Offset Drift vs. Temperature Parameter, Positive Full-Scale Drift vs. Temp. Parameter, and
2/03—Revision 0: Initial Version
Channel-to-Channel Isolation Parameter in Table 1... 3 Change to ADC Performance Chopping Disabled, Channel-to- Channel Isolation Parameter in Table 1 .. 3 Rev. A | Page 2 of 32 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM REVISION HISTORY AD7732—SPECIFICATIONS Table 1. (–40°C to +105°C; AVDD = 5 V ± 5%; DVDD = 2.7 V to 3.6 V, or 5 V ± 5%; BIAS (all), REFIN(+) = 2.5 V; REFIN(–) = AGND; RA, RB, RC, RD open circuit; AIN Range = ±10 V; fMCLKIN = 6.144 MHz; unless otherwise noted.) TIMING SPECIFICATIONS Table 2. (AVDD = 5 V ± 5%; DVDD = 2.7 V to 3.6 V, or 5 V ± 5%; Input Logic 0 = 0 V; Logic 1 = DVDD; unless otherwise noted.) ABSOLUTE MAXIMUM RATINGS Table 3. TA = 25°C, unless otherwise noted. TYPICAL PERFORMANCE CHARACTERISTICS OUTPUT NOISE AND RESOLUTION SPECIFICATION Chopping Enabled Table 4. Typical Output RMS Noise in µV vs. Conversion Time and Input Range with Chopping Enabled Table 5. Typical Effective Resolution in Bits vs. Conversion Time and Input Range with Chopping Enabled Table 6. Typical Peak-to-Peak Resolution in Bits vs. Conversion Time and Input Range with Chopping Enabled Chopping Disabled Table 7. Typical Output RMS Noise in µV vs. Conversion Time and Input Range with Chopping Disabled Table 8. Typical Effective Resolution in Bits vs. Conversion Time and Input Range with Chopping Disabled Table 9. Typical Peak-to-Peak Resolution in Bits vs. Conversion Time and Input Range with Chopping Disabled PIN CONFIGURATIONS AND FUNCTIONAL DESCRIPTIONS Table 10. Pin Function Descriptions—28-Lead TSSOP REGISTER DESCRIPTION Table 11. Register Summary Table 12. Operational Mode Summary Table 13. Input Range Summary Register Access Communications Register Table 14. I/O Port Register Revision Register Test Register ADC Status Register Checksum Register ADC Zero-Scale Calibration Register ADC Full-Scale Register Channel Data Registers Channel Zero-Scale Calibration Registers Channel Full-Scale Calibration Registers Channel Status Registers Channel Setup Registers Table 15. Channel Conversion Time Registers Mode Register DIGITAL INTERFACE DESCRIPTION Hardware Reset Access the AD7732 Registers Single Conversion and Reading Data Dump Mode Continuous Conversion Mode Continuous Read (Continuous Conversion) Mode CIRCUIT DESCRIPTION Analog Front End Analog Input’s Extended Voltage Range Table 16. Extended Input Voltage Range, Nominal Voltage Range ±10 V, 16 Bits, CLAMP = 0 Table 17. Extended Input Voltage Range, Nominal Voltage Range 0 V to +10 V, 16 Bits, CLAMP = 0 Chopping Multiplexer, Conversion, and Data Output Timing Sigma-Delta ADC Frequency Response Voltage Reference Inputs Reference Detect I/O Port Calibration ADC Zero-Scale Self-Calibration Per Channel System Calibration High Common-Mode Voltage Application OUTLINE DIMENSIONS Ordering Guide
AD7732 TABLE OF CONTENTS
AD7732—Specifications.. 3 Digital Interface Description .. 22 Timing Specifications... 6 Hardware ... 22 Absolute Maximum Ratings.. 8 Reset ... 23 Typical Performance Characteristics ... 9 Access the AD7732 Registers.. 23 Output Noise and Resolution Specification.. 10 Single Conversion and Reading Data .. 23 Chopping Enabled.. 10 Dump Mode.. 24 Chopping Disabled... 11 Continuous Conversion Mode ... 24 Pin Configurations and Functional Descriptions .. 12 Continuous Read (Continuous Conversion) Mode .. 25 Register Description... 14 Circuit Description... 26 Register Access.. 15 Analog Front End... 26 Communications Register... 15 Analog Input’s Extended Voltage Range ... 27 I/O Port Register... 16 Chopping ... 27 Revision Register .. 16 Multiplexer, Conversion, and Data Output Timing ... 28 Test Register .. 16 Sigma-Delta ADC .. 28 ADC Status Register... 17 Frequency Response .. 28 Checksum Register... 17 Voltage Reference Inputs... 29 ADC Zero-Scale Calibration Register ... 17 Reference Detect... 29 ADC Full-Scale Register.. 17 I/O Port.. 30 Channel Data Registers.. 17 Calibration... 30 Channel Zero-Scale Calibration Registers .. 18 ADC Zero-Scale Self-Calibration .. 30 Channel Full-Scale Calibration Registers.. 18 Per Channel System Calibration .. 30 Channel Status Registers ... 18 High Common-Mode Voltage Application .. 31 Channel Setup Registers .. 19 Outline Dimensions ... 32 Channel Conversion Time Registers ... 19 Ordering Guide .. 32 Mode Register ... 20
REVISION HISTORY 6/11—Rev. 0 to Rev. A
Changes to Figure 22.. 25 Changes to ADC Performance Chopping Enabled, Offset Error Changes to Ordering Guide .. 32 (Unipolar, Bipolar) Parameter, Offset Drift vs. Temperature Parameter, Positive Full-Scale Drift vs. Temp. Parameter, and
2/03—Revision 0: Initial Version
Channel-to-Channel Isolation Parameter in Table 1... 3 Change to ADC Performance Chopping Disabled, Channel-to- Channel Isolation Parameter in Table 1 .. 3 Rev. A | Page 2 of 32 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM REVISION HISTORY AD7732—SPECIFICATIONS Table 1. (–40°C to +105°C; AVDD = 5 V ± 5%; DVDD = 2.7 V to 3.6 V, or 5 V ± 5%; BIAS (all), REFIN(+) = 2.5 V; REFIN(–) = AGND; RA, RB, RC, RD open circuit; AIN Range = ±10 V; fMCLKIN = 6.144 MHz; unless otherwise noted.) TIMING SPECIFICATIONS Table 2. (AVDD = 5 V ± 5%; DVDD = 2.7 V to 3.6 V, or 5 V ± 5%; Input Logic 0 = 0 V; Logic 1 = DVDD; unless otherwise noted.) ABSOLUTE MAXIMUM RATINGS Table 3. TA = 25°C, unless otherwise noted. TYPICAL PERFORMANCE CHARACTERISTICS OUTPUT NOISE AND RESOLUTION SPECIFICATION Chopping Enabled Table 4. Typical Output RMS Noise in µV vs. Conversion Time and Input Range with Chopping Enabled Table 5. Typical Effective Resolution in Bits vs. Conversion Time and Input Range with Chopping Enabled Table 6. Typical Peak-to-Peak Resolution in Bits vs. Conversion Time and Input Range with Chopping Enabled Chopping Disabled Table 7. Typical Output RMS Noise in µV vs. Conversion Time and Input Range with Chopping Disabled Table 8. Typical Effective Resolution in Bits vs. Conversion Time and Input Range with Chopping Disabled Table 9. Typical Peak-to-Peak Resolution in Bits vs. Conversion Time and Input Range with Chopping Disabled PIN CONFIGURATIONS AND FUNCTIONAL DESCRIPTIONS Table 10. Pin Function Descriptions—28-Lead TSSOP REGISTER DESCRIPTION Table 11. Register Summary Table 12. Operational Mode Summary Table 13. Input Range Summary Register Access Communications Register Table 14. I/O Port Register Revision Register Test Register ADC Status Register Checksum Register ADC Zero-Scale Calibration Register ADC Full-Scale Register Channel Data Registers Channel Zero-Scale Calibration Registers Channel Full-Scale Calibration Registers Channel Status Registers Channel Setup Registers Table 15. Channel Conversion Time Registers Mode Register DIGITAL INTERFACE DESCRIPTION Hardware Reset Access the AD7732 Registers Single Conversion and Reading Data Dump Mode Continuous Conversion Mode Continuous Read (Continuous Conversion) Mode CIRCUIT DESCRIPTION Analog Front End Analog Input’s Extended Voltage Range Table 16. Extended Input Voltage Range, Nominal Voltage Range ±10 V, 16 Bits, CLAMP = 0 Table 17. Extended Input Voltage Range, Nominal Voltage Range 0 V to +10 V, 16 Bits, CLAMP = 0 Chopping Multiplexer, Conversion, and Data Output Timing Sigma-Delta ADC Frequency Response Voltage Reference Inputs Reference Detect I/O Port Calibration ADC Zero-Scale Self-Calibration Per Channel System Calibration High Common-Mode Voltage Application OUTLINE DIMENSIONS Ordering Guide