Datasheet AD7732 (Analog Devices) - 6

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AD7732 Parameter Min Typ Max Unit Test Conditions/Comments
Power Dissipation (Normal Mode) 14 85 100 mW AVDD+DVDD Current (Standby Mode)15 140 μA Power Dissipation (Standby Mode)15 750 μW 1 Specifications are not production tested but guaranteed by design and/or characterization data at initial product release. 2 See Typical Performance Characteristics. 3 VCM = Common-Mode Voltage = 0 V. 4 Specifications before calibration. Channel system calibration reduces these errors to the order of the noise. 5 Applies after the zero-scale and full-scale calibration. The negative full-scale error represents the remaining error after removing the offset and gain error. 6 ADC zero-scale self-calibration reduces this error to ±10 mV. Channel zero-scale system calibration reduces this error to the order of the noise. 7 For specified performance. The output data span corresponds to the specified nominal input voltage range. The ADC is functional outside the nominal input voltage range, but the performance might degrade. Outside the nominal input voltage range, the OVR bit in the channel status register is set and the channel data register value depends on the CLAMP bit in the mode register. See the register and circuit descriptions for more details. 8 The AIN absolute voltage of ±16.5 V applies for a nominal VBIAS voltage of +2.5 V. By configuring the BIAS and RA to RD pins differently, the part will work with higher AIN absolute voltages as long as the internal voltage seen by the multiplexer and the input buffer is within 200 mV to AVDD – 300 mV. Absolute voltage for the AIN, BIAS, and RA to RD pins must never exceed the values specified in the Absolute Maximum Ratings. 9 Pin impedance is from the pin to the internal node. In normal circuit configuration, the analog input total impedance is typically 108.5 kΩ + 15.5 kΩ = 124 kΩ. 10 For specified performance. Part is functional with lower VREF. 11 Dynamic current charging the sigma-delta modulator input switching capacitor. 12 Outside the specified calibration range, calibration is possible but the performance may degrade. 13 These logic output levels apply to the MCLK OUT output when it is loaded with a single CMOS load. 14 With external MCLK, MCLKOUT is disabled (the CLKDIS bit is set in the mode register). 15 External MCLKIN = 0 V or DVDD, Digital Inputs = 0 V or DVDD, and P0 and P1 = 0 V or AVDD. Rev. A | Page 5 of 32 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM REVISION HISTORY AD7732—SPECIFICATIONS Table 1. (–40°C to +105°C; AVDD = 5 V ± 5%; DVDD = 2.7 V to 3.6 V, or 5 V ± 5%; BIAS (all), REFIN(+) = 2.5 V; REFIN(–) = AGND; RA, RB, RC, RD open circuit; AIN Range = ±10 V; fMCLKIN = 6.144 MHz; unless otherwise noted.) TIMING SPECIFICATIONS Table 2. (AVDD = 5 V ± 5%; DVDD = 2.7 V to 3.6 V, or 5 V ± 5%; Input Logic 0 = 0 V; Logic 1 = DVDD; unless otherwise noted.) ABSOLUTE MAXIMUM RATINGS Table 3. TA = 25°C, unless otherwise noted. TYPICAL PERFORMANCE CHARACTERISTICS OUTPUT NOISE AND RESOLUTION SPECIFICATION Chopping Enabled Table 4. Typical Output RMS Noise in µV vs. Conversion Time and Input Range with Chopping Enabled Table 5. Typical Effective Resolution in Bits vs. Conversion Time and Input Range with Chopping Enabled Table 6. Typical Peak-to-Peak Resolution in Bits vs. Conversion Time and Input Range with Chopping Enabled Chopping Disabled Table 7. Typical Output RMS Noise in µV vs. Conversion Time and Input Range with Chopping Disabled Table 8. Typical Effective Resolution in Bits vs. Conversion Time and Input Range with Chopping Disabled Table 9. Typical Peak-to-Peak Resolution in Bits vs. Conversion Time and Input Range with Chopping Disabled PIN CONFIGURATIONS AND FUNCTIONAL DESCRIPTIONS Table 10. Pin Function Descriptions—28-Lead TSSOP REGISTER DESCRIPTION Table 11. Register Summary Table 12. Operational Mode Summary Table 13. Input Range Summary Register Access Communications Register Table 14. I/O Port Register Revision Register Test Register ADC Status Register Checksum Register ADC Zero-Scale Calibration Register ADC Full-Scale Register Channel Data Registers Channel Zero-Scale Calibration Registers Channel Full-Scale Calibration Registers Channel Status Registers Channel Setup Registers Table 15. Channel Conversion Time Registers Mode Register DIGITAL INTERFACE DESCRIPTION Hardware Reset Access the AD7732 Registers Single Conversion and Reading Data Dump Mode Continuous Conversion Mode Continuous Read (Continuous Conversion) Mode CIRCUIT DESCRIPTION Analog Front End Analog Input’s Extended Voltage Range Table 16. Extended Input Voltage Range, Nominal Voltage Range ±10 V, 16 Bits, CLAMP = 0 Table 17. Extended Input Voltage Range, Nominal Voltage Range 0 V to +10 V, 16 Bits, CLAMP = 0 Chopping Multiplexer, Conversion, and Data Output Timing Sigma-Delta ADC Frequency Response Voltage Reference Inputs Reference Detect I/O Port Calibration ADC Zero-Scale Self-Calibration Per Channel System Calibration High Common-Mode Voltage Application OUTLINE DIMENSIONS Ordering Guide