Datasheet AD9200 (Analog Devices) - 4

AD9200 Parameter Symbol Min Typ Max Units Condition
DIGITAL INPUTS High Input Voltage VIH 2.4 V Low Input Voltage VIL 0.3 V DIGITAL OUTPUTS High-Z Leakage IOZ –10 +10 µA Output = GND to VDD Data Valid Delay tOD 25 ns CL = 20 pF Data Enable Delay tDEN 25 ns Data High-Z Delay tDHZ 13 ns LOGIC OUTPUT (with DRVDD = 3 V) High Level Output Voltage (IOH = 50 µA) VOH +2.95 V High Level Output Voltage (IOH = 0.5 mA) VOH +2.80 V Low Level Output Voltage (IOL = 1.6 mA) VOL +0.4 V Low Level Output Voltage (IOL = 50 µA) VOL +0.05 V LOGIC OUTPUT (with DRVDD = 5 V) High Level Output Voltage (IOH = 50 µA) VOH +4.5 V High Level Output Voltage (IOH = 0.5 mA) VOH +2.4 V Low Level Output Voltage (IOL = 1.6 mA) VOL +0.4 V Low Level Output Voltage (IOL = 50 µA) VOL +0.1 V CLOCKING Clock Pulsewidth High tCH 22.5 ns Clock Pulsewidth Low tCL 22.5 ns Pipeline Latency 3 Cycles CLAMP2 Clamp Error Voltage E ± OC 20 ±40 mV CLAMPIN = 0.5 V–2.7 V, RIN = 10 Ω Clamp Pulsewidth tCPW 2 µs CIN = 1 µF (Period = 63.5 µs) NOTES 1See Figures 1a and 1b. 2Available only in AD9200ARS and AD9200KST. Specifications subject to change without notice.
REFTS 10k
V
REFTS AD9200 AD9200 REFTF 4.2k
V
10k
V
REFBS REFBF 0.4
3
VDD REFBS MODE AV MODE DD
Figure 1a. Figure 1b. REV. E –3–