Datasheet MCP3202 (Microchip) - 3

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MCP3202 ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Characteristics:
Unless otherwise noted, all parameters apply at VDD = 5.5V, VSS = 0V, TA = -40°C to +85°C, fSAMPLE = 100 ksps and fCLK = 18*fSAMPLE.
Parameter Sym Min. Typ. Max. Units Conditions
High Level Output Voltage VOH 4.1 — — V IOH = -1 mA, VDD = 4.5V Low Level Output Voltage VOL — — 0.4 V IOL = 1 mA, VDD = 4.5V Input Leakage Current ILI -10 — 10 µA VIN = VSS or VDD Output Leakage Current ILO -10 — 10 µA VOUT = VSS or VDD Pin Capacitance CIN, COUT — — 10 pF VDD = 5.0V (
Note 1
) (All Inputs/Outputs) TA = +25°C, f = 1 MHz
Timing Parameters:
Clock Frequency fCLK — — 1.8 MHz VDD = 5V (
Note 2
) 0.9 MHz VDD = 2.7V (
Note 2
) Clock High Time tHI — 2 MHz Clock Low Time tLO — 2 MHz CS Fall To First Rising CLK tSUCS 100 — — ns Edge Data Input Setup Time tSU 50 — — ns Data Input Hold Time tHD 50 — — ns CLK Fal To Output Data Valid tDO — — 200 ns See Test Circuits, Figure 1-2 CLK Fall To Output Enable tEN — — 200 ns See Test Circuits, Figure 1-2 CS Rise To Output Disable tDIS — — 100 ns See Test Circuits, Figure 1-2 Note 1 CS Disable Time tCSH 500 — — ns DOUT Rise Time tR — — 100 ns See Test Circuits, Figure 1-2 Note 1 DOUT Fall Time tF — — 100 ns See Test Circuits, Figure 1-2 Note 1
Power Requirements:
Operating Voltage VDD 2.7 — 5.5 V Operating Current IDD — 375 550 µA VDD = 5.0V, DOUT unloaded Standby Current IDDS — 0.5 5 µA CS = VDD = 5.0V
Note 1:
This parameter is established by characterization and not 100% tested.
2:
Because the sample cap will eventually lose charge, effective clock rates below 10 kHz can affect linearity performance, especially at elevated temperatures. See
Section 6.2 “Maintaining Minimum Clock Speed”
for more information.
TEMPERATURE CHARACTERISTICS Electrical Specifications:
Unless otherwise indicated, VDD = +2.7V to +5.5V, VSS = GND.
Parameters Sym Min Typ Max Units Conditions Temperature Ranges
Specified Temperature Range TA -40 — +85 °C Operating Temperature Range TA -40 — +85 °C Storage Temperature Range TA -65 — +150 °C
Thermal Package Resistances
Thermal Resistance, 8L-MSOP JA — 211 — °C/W Thermal Resistance, 8L-PDIP JA — 89.5 — °C/W Thermal Resistance, 8L-SOIC JA — 149.5 — °C/W Thermal Resistance, 8L-TSSOP JA — 139 — °C/W  1999-2011 Microchip Technology Inc. DS21034F-page 3 Document Outline MCP3202 - 2.7V Dual Channel 12-Bit A/D Converter with SPI Serial Interface Functional Block Diagram Package Types 1.0 Electrical Characteristics Absolute Maximum Ratings † FIGURE 1-1: Serial Timing. FIGURE 1-2: Test Circuits. 2.0 Typical Performance Characteristics FIGURE 2-1: Integral Nonlinearity (INL) vs. Sample Rate. FIGURE 2-2: Integral Nonlinearity (INL) vs. VDD. FIGURE 2-3: Integral Nonlinearity (INL) vs. Code (Representative Part). FIGURE 2-4: Integral Nonlinearity (INL) vs. Sample Rate (VDD = 2.7V). FIGURE 2-5: Integral Nonlinearity (INL) vs. VDD. FIGURE 2-6: Integral Nonlinearity (INL) vs. Code (Representative Part, VDD = 2.7V). FIGURE 2-7: Integral Nonlinearity (INL) vs. Temperature. FIGURE 2-8: Differential Nonlinearity (DNL) vs. Sample Rate. FIGURE 2-9: Differential Nonlinearity (DNL) vs. VDD. FIGURE 2-10: Integral Nonlinearity (INL) vs. Temperature (VDD = 2.7V). FIGURE 2-11: Differential Nonlinearity (DNL) vs. Sample Rate (VDD = 2.7V). FIGURE 2-12: Differential Nonlinearity (DNL) vs. VDD. FIGURE 2-13: Differential Nonlinearity (DNL) vs. Code (Representative Part). FIGURE 2-14: Differential Nonlinearity (DNL) vs. Temperature. FIGURE 2-15: Gain Error vs. VDD. FIGURE 2-16: Differential Nonlinearity (DNL) vs. Code (Representative Part, VDD = 2.7V). FIGURE 2-17: Differential Nonlinearity (DNL) vs. Temperature (VDD = 2.7V). FIGURE 2-18: Offset Error vs. VDD. FIGURE 2-19: Gain Error vs. Temperature. FIGURE 2-20: Signal-to-Noise Ratio (SNR) vs. Input Frequency. FIGURE 2-21: Total Harmonic Distortion (THD) vs. Input Frequency. FIGURE 2-22: Offset Error vs. Temperature. FIGURE 2-23: Signal-to-Noise and Distortion (SINAD) vs. Input Frequency. FIGURE 2-24: Signal-to-Noise and Distortion (SINAD) vs. Signal Level. FIGURE 2-25: Effective Number of Bits (ENOB) vs. VDD. FIGURE 2-26: Spurious Free Dynamic Range (SFDR) vs. Input Frequency. FIGURE 2-27: Frequency Spectrum of 10 kHz input (Representative Part). FIGURE 2-28: Effective Number of Bits (ENOB) vs. Input Frequency. FIGURE 2-29: Power Supply Rejection (PSR) vs. Ripple Frequency. FIGURE 2-30: Frequency Spectrum of 1 kHz input (Representative Part, VDD = 2.7V). FIGURE 2-31: IDD vs. VDD. FIGURE 2-32: IDD vs. Clock Frequency. FIGURE 2-33: IDD vs. Temperature. FIGURE 2-34: IDDS vs. VDD. FIGURE 2-35: IDDS vs. Temperature. FIGURE 2-36: Analog Input leakage current vs. Temperature. 3.0 Pin Descriptions TABLE 3-1: Pin Function Table 3.1 Analog Inputs (CH0/CH1) 3.2 Chip Select/Shutdown (CS/SHDN) 3.3 Serial Clock (CLK) 3.4 Serial Data Input (DIN) 3.5 Serial Data Output (DOUT) 4.0 Device Operation 4.1 Analog Inputs 4.2 Digital Output Code EQUATION 4-1: FIGURE 4-1: Analog Input Model. FIGURE 4-2: Maximum Clock Frequency vs. Input Resistance (RS) to maintain less than a 0.1 LSB deviation in INL from nominal conditions. 5.0 Serial Communications 5.1 Overview TABLE 5-1: Configuration Bits for the MCP3202 FIGURE 5-1: Communication with the MCP3202 using MSB first format only. FIGURE 5-2: Communication with MCP3202 using LSB first format. 6.0 Applications Information 6.1 Using the MCP3202 with Microcontroller (MCU) SPI Ports FIGURE 6-1: SPI Communication using 8-bit segments (Mode 0,0: SCLK idles low). FIGURE 6-2: SPI Communication using 8-bit segments (Mode 1,1: SCLK idles high). 6.2 Maintaining Minimum Clock Speed 6.3 Buffering/Filtering the Analog Inputs FIGURE 6-3: The MCP601 Operational Amplifier is used to implement a 2nd order anti- aliasing filter for the signal being converted by the MCP3202. 6.4 Layout Considerations FIGURE 6-4: VDD traces arranged in a ‘Star’ configuration in order to reduce errors caused by current return paths. 7.0 Packaging Information 7.1 Package Marking Information Appendix A: Revision History Worldwide Sales and Service