Datasheet LTC4306 (Analog Devices) - 9

LTC4306
U OPERATIO Register 2 (02h) Register 3 (03h) BIT NAME TYPE* DESCRIPTION BIT NAME TYPE* DESCRIPTION
d7 GPIO1 Mode R/W Configures Input/Output mode of d7 Bus 1 FET State R/W Sets and indicates state of FET Configure GPIO1 switches connected to downstream 0 = output mode (default) bus 1 1 = input mode 0 = switch open (default) d6 GPIO2 Mode R/W Configures Input/Output Mode of 1 = switch closed Configure GPIO2 d6 Bus 2 FET State R/W Sets and indicates state of FET 0 = output mode (default) switches connected to downstream 1 = input mode bus 2 d5 Connection R/W Sets logic requirements for 0 = switch open (default) Requirement downstream buses to be connected 1 = switch closed to upstream bus d5 Bus 3 FET State R/W Sets and indicates state of FET 0 = Bus Logic State bits (see register switches connected to downstream 3) of buses to be connected must be bus 3 high for connection to occur (default) 0 = switch open (default) 1 = Connect regardless of 1 = switch closed downstream logic state d4 Bus 4 FET State R/W Sets and indicates state of FET d4 GPIO1 Output R/W Configures GPIO1 Output Mode switches connected to downstream Mode Configure 0 = open-drain pull-down (default) bus 4 1 = push-pull 0 = switch open (default) d3 GPIO2 Output R/W Configures GPIO2 Output Mode 1 = switch closed Mode Configure 0 = open-drain pull-down (default) d3 Bus 1 Logic State R Indicates logic state of downstream 1 = push-pull bus 1; only valid when disconnected d2 Mass Write Enable R/W Enable Mass Write Address using from upstream bus† address (1011 101)b 0 = SDA1, SCL1 or both are below 1V 0 = Disable Mass Write 1 = SDA1 and SCL1 are both above 1 = Enable Mass Write (default) 1V d1 Timeout Mode Bit 1 R/W Stuck Low Timeout Set Bit 1** d2 Bus 2 Logic State R Indicates logic state of downstream bus 2; only valid when disconnected d0 Timeout Mode Bit 0 R/W Stuck Low Timeout Set Bit 0** from upstream bus† * For Type, “R/W” = Read Write, “R” = Read Only 0 = SDA2, SCL2 or both are below 1V **Stuck bus program table 1 = SDA2 and SCL2 are both above
TIMSET1 TIMSET0 TIMEOUT MODE
1V 0 0 Timeout Disabled (Default) d1 Bus 3 Logic State R Indicates logic state of downstream bus 3; only valid when disconnected 0 1 Timeout After 30ms from upstream bus† 1 0 Timeout After 15ms 0 = SDA3, SCL3 or both are below 1V 1 1 Timeout After 7.5ms 1 = SDA3 and SCL3 are both above 1V d0 Bus 4 Logic State R Indicates logic state of downstream bus 4; only valid when disconnected from upstream bus† 0 = SDA4, SCL4 or both are below 1V 1 = SDA4 and SCL4 are both above 1V * For Type, “R/W” = Read Write, “R” = Read Only † These bits give the logic state of disconnected downstream buses to the master, so that the master can choose not to connect to a low downstream bus. A given bit is a “don’t care” if its associated downstream bus is already connected to the upstream bus. 4306f 9