Datasheet LTC4306 (Analog Devices) - 10

LTC4306
U OPERATIO
The LTC4306 is a 4-channel, 2-wire bus multiplexer/ commanding connection to one or more downstream switch with bus buffers to provide capacitive isolation channels, and second, there must be no stuck low between the upstream bus and downstream buses. Mas- condition (see Stuck Low Timeout Fault discussion). If ters on the upstream 2-wire bus (SDAIN and SCLIN) can the connection command is successful, the Upstream- command the LTC4306 to any combination of the 4 Downstream Buffers pass signals between the upstream downstream buses. Masters can also program the LTC4306 bus and the connected downstream buses. The LTC4306 to disconnect the upstream bus from the downstream also turns off its N-channel MOSFET open-drain pull- buses if the bus is stuck low. down on the READY pin, so that READY can be pulled high by its external pull-up resistor.
Undervoltage Lockout (UVLO) and ENABLE Functionality Upstream-Downstream Buffers
The LTC4306 contains undervoltage lockout circuitry that Once the Upstream-Downstream Buffers are activated, maintains all of its SDA, SCL, GPIO and ALERT pins in high the functionality of the SDAIN and any connected down- impedance states until the device has sufficient V stream SDA pins is identical. A low forced on any con- CC supply voltage to function properly. It also ignores any attempts nected SDA pin at any time results in all pins being low. to communicate with it via the 2-wire buses in this condi-
External devices must pull the pin voltages below 0.4V
tion. When the ENABLE pin voltage is low (below 0.8V), all
worst-case with respect to the LTC4306’s ground pin to
control bits are reset to their default high impedance
ensure proper operation.
The SDA pins enter a logic high states, and the LTC4306 ignores 2-wire bus commands. state only when all devices on all connected SDA pins force However, with ENABLE low, the LTC4306 still monitors a high. The same is true for SCLIN and the connected the ALERT1-ALERT4 pin voltages and pulls the ALERT pin downstream SCL pins. This important feature ensures low if any of ALERT1-ALERT4 is low. When ENABLE is that clock stretching, clock arbitration and the acknowl- high, devices can read from and write to the LTC4306. edge protocol always work, regardless of how the devices in the system are connected to the LTC4306.
Connection Circuitry
The Upstream-Downstream Buffers provide capacitive Masters on the upstream SDAIN/SCLIN bus can write to isolation between SDAIN/SCLIN and the downstream con- the Bus 1 FET State through Bus 4 FET State bits of register nected buses. Note that there is no capacitive isolation 3 to connect to any combination of downstream channels between connected downstream buses; they are only 1 to 4. By default, the Connection Circuitry shown in the separated by the series combination of their switches’ on Block Diagram will only connect to downstream channels resistances. whose corresponding Bus Logic State bits in register 3 are While any combination of downstream buses may be high at the moment that it receives the connection com- connected at the same time, logic high levels are corrupted mand. If the LTC4306 is commanded to connect to mul- if multiple downstream buses are active and both the VCC tiple channels at once, it will only connect to the channels voltage and one or more downstream bus pull-up voltages that are high. Masters can override this feature by setting are larger than the pull-up supply voltage for another the Connection Requirement bit of register 2 high. With downsteam bus. An example of this issue is shown in this bit high, the LTC4306 executes connection com- Figure 1. During logic highs, DC current flows from VBUS1 mands without regard to the logic states of the down- through the series combination of R1, N1, N2 and R2 and stream channels. into VBUS2, causing the SDA1 voltage to drop and current Upon receiving the connection command, the Connec- to be sourced into VBUS2. To avoid this problem, do not tion Circuitry will activate the Upstream-Downstream activate bus 1 or any other downstream bus whose pull- Buffers under two conditions: first, the master must be up voltage is above 2.5V when bus 2 is active. 4306f 10