Datasheet AD5748 (Analog Devices) - 5

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Data Sheet AD5748 Parameter 1 Min Typ Max Unit Test Conditions/Comments
Output Noise Spectral Density 165 nV/√Hz Measured at 10 kHz; specified with 2 kΩ || 220 pF AC PSRR −65 dB 200 mV, 50 Hz/60 Hz sine wave superimposed on power supply voltage DC PSRR 10 µV/V Outputs unloaded CURRENT OUTPUT, IOUT Output Current Ranges 0 21 mA 4 21 mA Accuracy, Internal R 4 SET Total Unadjusted Error (TUE)2 −0.5 +0.5 % FSR −0.3 ±0.15 +0.3 % FSR TA = 25°C Relative Accuracy (INL) −0.02 ±0.01 +0.02 % FSR 4 mA to 21 mA, 0 mA to 21 mA Offset Error −16 +16 µA 4 mA to 21 mA, 0 mA to 21 mA −10 +5 +10 µA TA = 25°C Offset Error TC3 ±3 ppm FSR/°C 4 mA to 21 mA, 0 mA to 21 mA Gain Error −0.2 +0.2 % FSR 4 mA to 21 mA, 0 mA to 21 mA −0.03 ±0.006 +0.03 % FSR TA = 25°C Gain TC3 ±8 ppm FSR/°C 4 mA to 21 mA, 0 mA to 21 mA Full-Scale Error −0.2 +0.2 % FSR 4 mA to 21 mA, 0 mA to 21 mA −0.125 ±0.02 +0.125 % FSR TA = 25°C Full-Scale TC3 ±4 ppm FSR/°C 4 mA to 21 mA, 0 mA to 21 mA Accuracy, External R 4 SET Total Unadjusted Error (TUE)2 −0.3 +0.3 % FSR −0.1 ±0.02 +0.1 % FSR TA = 25°C Relative Accuracy (INL) −0.02 ±0.01 +0.02 % FSR 4 mA to 21 mA, 0 mA to 21 mA Offset Error −14 +14 µA 4 mA to 21 mA, 0 mA to 21 mA −11 +5 +11 µA TA = 25°C Offset Error TC3 ±2 ppm FSR/°C 4 mA to 21 mA, 0 mA to 21 mA Gain Error −0.08 +0.08 % FSR 4 mA to 21 mA, 0 mA to 21 mA −0.07 ±0.02 +0.07 % FSR TA = 25°C Gain TC ±1 ppm FSR/°C 4 mA to 21 mA, 0 mA to 21 mA Full-Scale Error −0.1 +0.1 % FSR 4 mA to 21 mA, 0 mA to 21 mA −0.07 ±0.02 +0.07 % FSR TA = 25°C Full-Scale TC3 ±2 ppm FSR/°C 4 mA to 21 mA, 0 mA to 21 mA CURRENT OUTPUT CHARACTERISTICS3 Current Loop Compliance Voltage 0 AVDD − 2.75 V Resistive Load See comments Chosen so that compliance is not exceeded Inductive Load See comments Needs appropriate capacitor at higher inductance values; see the Driving Inductive Loads section Settling Time 4 mA to 21 mA, Full-Scale Step 8.5 µs 250 Ω load 120 µA Step, 4 mA to 21 mA Range 1.2 µs 250 Ω load DC PSRR 1 µA/V Output Impedance 130 MΩ DIGITAL INPUT JEDEC compliant Input High Voltage, VIH 2 V Input Low Voltage, VIL 0.8 V Input Current −1 +1 µA Per pin Pin Capacitance 5 pF Per pin DIGITAL OUTPUTS3 FAULT, IFAULT, TEMP, VFAULT Output Low Voltage, VOL 0.4 V 10 kΩ pull-up resistor to DVCC Output Low Voltage, VOL 0.6 V At 2.5 mA Output High Voltage, VOH 3.6 V 10 kΩ pull-up resistor to DVCC Rev. B | Page 5 of 32 Document Outline Features Applications General Description Table of Contents Revision History Functional Block Diagram Specifications Timing Characteristics Timing Diagrams Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Voltage Output Current Output Terminology Theory of Operation Software Mode Current Output Architecture Driving Inductive Loads Voltage Output Amplifier Driving Large Capacitive Loads Power-On State of the AD5748 Default Registers at Power-On Reset Function OUTEN Software Control Input Shift Register Readback Operation Hardware Control Transfer Function Detailed Description of Features Output Fault Alert—Software Mode Output Fault Alert—Hardware Mode Voltage Output Short-Circuit Protection Asynchronous Clear (CLEAR) Current Setting Resistor Packet Error Checking Applications Information Transient Voltage Protection Thermal Considerations Layout Guidelines Galvanically Isolated Interface Microprocessor Interfacing Outline Dimensions Ordering Guide