Datasheet ADM1041A (Analog Devices) - 6

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ADM1041A SPECIFICATIONS
TA = –40 to +85°C, VDD = 5 V ± 10%, unless otherwise noted.
Table 1. Parameter Min Typ Max Unit Test Conditions/Comments
SUPPLIES VDD 4.5 5.0 5.5 V IDD, Current Consumption 6 10 mA Peak IDD, during EEPROM Erase Cycle1, 2 40 mA UNDERVOLTAGE LOCKOUT, VDD See Figure 9. Start-Up Threshold 4 4.3 4.5 V Stop Threshold 3.7 4 4.2 V Hysteresis 0.3 V POWER BLOCK PROTECTION VDD Overvoltage 5.8 6.2 6.5 V VDD Overvoltage Debounce 300 500 700 μs Latching Open Ground 0.1 0.2 0.35 V VGND positive with respect to VS− VDDOK Debounce 250 400 500 μs VDDOK POWER-ON RESET DC Level 1.5 2.2 2.75 V VDD rising DIFFERENTIAL LOAD VOLTAGE SENSE INPUT, See Figure 6. VNOM = (VS+ – VS−); VNOM (VS−, VS+) is typically 2 V VS− Input Voltage 0.5 V Voltage on Pin 20 VS+ Input Voltage VDD – 2 V Voltage on Pin 21 VS− Input Resistance 35 kΩ VS+ Input Resistance 500 kΩ VNOM Adjustment Range 1.7 to 2.3 V Set Load Voltage Trim Step 0.10 to 0.14 % 1.7 V ≤ VNOM ≤ 2.3 V typ 1.74 to 3.18 mV 8 bits, 255 steps Reg 19h[7:0]. See Table 34 Set Load Overvoltage Trim Range 105 to 120 % 1.7 V ≤ VNOM ≤ 2.3 V min Set Load Overvoltage Trim Step 0.09 % 8 bits, 255 step/s 1.6 mV Reg 08h[7:0]. See Table 17. VS+ = 2.24 V Recover from Load OV False to FG True 100 μs Reg 03h[1:0] = 00. See Table 12. 200 μs Reg 03h[1:0] = 01. See Table 12. 300 μs Reg 03h[1:0] = 10. See Table 12. 400 μs Reg 03h[1:0] = 11. See Table 12. Operate Time from Load OV to FG False 2 μs Rev. 0 | Page 6 of 56 Document Outline FEATURES SECONDARY-SIDE FEATURES INTERFACE AND INTERNAL FEATURES APPLICATIONS GENERAL DESCRIPTION SAMPLE APPLICATION CIRCUIT DESCRIPTION SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TERMINOLOGY THEORY OF OPERATION POWER MANAGEMENT GAIN TRIMMING AND CONFIGURATION DIFFERENTIAL REMOTE SENSE AMPLIFIER SET LOAD VOLTAGE LOAD OVERVOLTAGE (OV) LOCAL VOLTAGE SENSE LOCAL OVERVOLTAGE PROTECTION (OVP) LOCAL UNDERVOLTAGE PROTECTION (UVP) FALSE UV CLAMP VOLTAGE ERROR AMPLIFIER MAIN VOLTAGE REFERENCE CURRENT-SENSE AMPLIFIER CURRENT SENSING CURRENT-TRANSFORMER INPUT CURRENT-SENSE CALIBRATION CURRENT-LIMIT ERROR AMPLIFIER OVERCURRENT PROTECTION CURRENT SHARE CURRENT-SHARE OFFSET ISHARE DRIVE AMPLIFIER DIFFERENTIAL SENSE AMPLIFIER ISHARE ERROR AMPLIFIER ISHARE CLAMP SHARE_OK DETECTOR PULSE/ACSENSE2 PULSE ACSENSE OrFET GATE DRIVE OSCILLATOR AND TIMING GENERATORS LOGIC I/O AND MONITOR PINS CBD/ALERT MON1 MON2 PEN PSON MON3 DC_OK (POWER-OK, POWER Good, Etc.) MON4 AC_OK MON5 SMBus SERIAL PORT MICROPROCESSOR SUPPORT Interfacing Configuring for a Microprocessor BROADCASTING SMBus SERIAL INTERFACE GENERAL SMBus TIMING SMBus PROTOCOLS FOR RAM AND EEPROM SMBus Erase EEPROM Page Operations SMBus Write Operations Send Byte Write Byte/Word Block Write SMBus READ OPERATIONS Receive Byte Block Read Notes on SMBus Read Operations SMBus ALERT RESPONSE ADDRESS (ARA) SUPPORT FOR SMBus 1.1 LAYOUT CONSIDERATIONS POWER-UP AUTO-CONFIGURATION EXTENDED SMBus ADDRESSING SDA/PSONLINK SCL/AC_OKLink BACKDOOR ACCESS REGISTER LISTING DETAILED REGISTER DESCRIPTIONS MANUFACTURING DATA MICROPROCESSOR SUPPORT TEST NAME TABLE OUTLINE DIMENSIONS ORDERING GUIDE