Datasheet ADE7116, ADE7166, ADE7169, ADE7566, ADE7569 (Analog Devices) - 4

ADE7116/ADE7166/ADE7169/ADE7566/ADE7569 Data Sheet GENERAL DESCRIPTION
The ADE7116/ADE7166/ADE7169/ADE7566/ADE75691 The microprocessor functionality includes a single cycle 8052 integrate the Analog Devices, Inc., energy (ADE) metering IC core, a real-time clock with a power supply backup pin, an SPI analog front end and fixed function DSP solution with an or I2C interface, and a UART interface. The ready to use infor- enhanced 8052 MCU core, an RTC, an LCD driver, and al the mation from the ADE core reduces the program memory size peripherals to make an electronic energy meter with an LCD requirement, making it easy to integrate complicated design display in a single device. into 16 kB of flash memory. The ADE measurement core includes active, reactive, and apparent The ADE7116/ADE7166/ADE7169/ADE7566/ADE7569 also energy calculations, as well as voltage and current rms measure- include a 108-/104-segment LCD driver. In the ADE7166/ ments. This information is accessible for energy billing by using ADE7169/ADE7566/ADE7569, this driver generates voltages the built in energy scalars. Many power line supervisory features capable of driving LCDs up to 5 V. such as SAG, peak, and zero crossing are included in the energy measurement DSP to simplify energy meter design. 1 Patents pending.
FUNCTIONAL BLOCK DIAGRAMS 0) 0. P 1/ TA A 4 /INT 2 CCAL D 3 TA /T0 RL /FP 2 T A RT I/S X D 19 1/ 2 LK /T1 SO 25 E /FP 22 21 20 /OU OS P C S BCT xD P P P P IN K I/S F CF CF /M /MI /S /S RxD T F /T2 F F F /T2 F X 1 2 0 ( 1/ 2/ 3/ .4 .5 .6 .7 0/ 1/ 2/ .3 5/ 6/ 7/ .4 CL SO OS 2E 0. 0. 0. 0. 0 0 0 1. 1. 1. 1 1 1. 1. 1. RE CF CF SS S MI M T0 T1 T2 T P P P P P P0 P P P P P P P P P P 57 43 42 38 39 40 41 39 38 7 6 45 11 43 42 41 40 39 38 37 36 5 6 7 8 9 10 12 P2.0/FP18 13 P2.1/FP17 14 P2.2/FP16 SPI/I2C 3 × 16-BIT ADE7566/ADE7569 SERIAL COUNTER 44 P2.3 (SDEN/P2.3) 1.20V INTERFACE TIMERS 16 LCDVP2 REF 18 LCDVA 3V/5V LCD I + 17 LCDVB P 52 CHARGE PUMP PGA1 ADC 15 LCDVC I 53 – N 4 COM0 ENERGY ... ... MEASUREMENT V + 1 COM3 P 49 DSP 108-SEGMENT PGA2 ADC LCD DRIVER V 35 FP0 – N 50 . .. ... 20 FP15 SINGLE PROGRAM MEMORY CYCLE 14 FP16 16kB FLASH WATCHDOG 63 8052 DGND MCU TIMER 13 FP17 USER RAM 12 FP18 AGND 54 256 BYTES 11 FP19 TEMP TEMP SENSOR ADC USER XRAM 10 FP20 256 BYTES DOWNLOADER 9 FP21 BATTERY DEBUGGER V 58 8 FP22 BAT ADC VDCIN 7 FP23 ADC PLL 6 FP24 POWER SUPPLY POR N TOR UART CONTROL AND UART SERIAL 5 FP25 MONITORING -PI LA TIMER RTC 1 U OSC PORT LDO 55 FP26 LDO M E 1 FP27 2 FP28 64 60 61 62 59 56 51 44 36 37 47 46 48 45 N D A DD UT EA EN xD L1 L2 T0 T1 DCI V O INT INT T RxD IN IN
001
V W V V ESET TA TA S SD X X V R
06353- Figure 1. ADE7566/ADE7569 Functional Block Diagram Rev. C | Page 4 of 152 Document Outline GENERAL FEATURES ENERGY MEASUREMENT FEATURES MICROPROCESSOR FEATURES REVISION HISTORY GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAMS SPECIFICATIONS ENERGY METERING ANALOG PERIPHERALS DIGITAL INTERFACE TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS PERFORMANCE CURVES FOR THE ADE7169 AND ADE7569 ONLY TERMINOLOGY SPECIAL FUNCTION REGISTER (SFR) MAPPING POWER MANAGEMENT POWER MANAGEMENT REGISTER DETAILS Writing to the Interrupt Pins Configuration SFR (INTPR, Address 0xFF) Clearing the Scratch Pad Registers (SCRATCH1, Address 0xFB to SCRATCH4, Address 0xFE) Writing to the Power Control SFR (POWCON, Address 0xC5) POWER SUPPLY ARCHITECTURE BATTERY SWITCHOVER VDD to VBAT Switching from VBAT to VDD POWER SUPPLY MANAGEMENT (PSM) INTERRUPT Battery Switchover and Power Supply Restored PSM Interrupt VDCIN ADC PSM Interrupt VBAT Monitor PSM Interrupt VDCIN Monitor PSM Interrupt SAG Monitor PSM Interrupt USING THE POWER SUPPLY FEATURES OPERATING MODES PSM0 (NORMAL MODE) PSM1 (BATTERY MODE) PSM2 (SLEEP MODE) 3.3 V PERIPHERALS AND WAKE-UP EVENTS TRANSITIONING BETWEEN OPERATING MODES Automatic Battery Switchover (PSM0 to PSM1) Entering Sleep Mode (PSM1 to PSM2) Servicing Wake-Up Events (PSM2 to PSM1) Automatic Switch to VDD (PSM2 to PSM0) USING THE POWER MANAGEMENT FEATURES ENERGY MEASUREMENT ACCESS TO ENERGY MEASUREMENT SFRs ACCESS TO INTERNAL ENERGY MEASUREMENT REGISTERS Writing to the Internal Energy Measurement Registers Reading the Internal Energy Measurement Registers ENERGY MEASUREMENT REGISTERS ENERGY MEASUREMENT INTERNAL REGISTER DETAILS INTERRUPT STATUS/ENABLE SFRs ANALOG INPUTS ANALOG-TO-DIGITAL CONVERSION Antialiasing Filter ADC Transfer Function Current Channel ADC Voltage Channel ADC Channel Sampling FAULT DETECTION Channel Selection Indication Fault Indication Fault with Active Input Greater Than Inactive Input Fault with Inactive Input Greater Than Active Input Calibration Concerns di/dt CURRENT SENSOR AND DIGITAL INTEGRATOR FOR THE ADE7169/ADE7569 POWER QUALITY MEASUREMENTS Zero-Crossing Detection Zero-Crossing Timeout Period or Frequency Measurements Line Voltage SAG Detection SAG Level Set Peak Detection Peak Level Set Peak Level Record PHASE COMPENSATION RMS CALCULATION Current Channel RMS Calculation Current Channel RMS Offset Compensation Voltage Channel RMS Calculation Voltage Channel RMS Offset Compensation ACTIVE POWER CALCULATION Active Power Gain Calibration Active Power Offset Calibration Active Power Sign Detection Active Power No Load Detection ACTIVE ENERGY CALCULATION Integration Time Under Steady Load: Active Energy Active Energy Accumulation Modes Watt Signed Accumulation Mode Watt Positive Only Accumulation Mode Watt Absolute Accumulation Mode Active Energy Pulse Output Line Cycle Active Energy Accumulation Mode REACTIVE POWER CALCULATION (ADE7169/ADE7569) Reactive Power Gain Calibration Reactive Power Offset Calibration Sign of Reactive Power Calculation Reactive Power Sign Detection Reactive Power No Load Detection REACTIVE ENERGY CALCULATION (ADE7169/ADE7569) Integration Time Under Steady Load: Reactive Energy Reactive Energy Accumulation Modes Var Signed Accumulation Mode Var Antitamper Accumulation Mode Var Absolute Accumulation Mode Reactive Energy Pulse Output Line Cycle Reactive Energy Accumulation Mode APPARENT POWER CALCULATION Apparent Power Offset Calibration APPARENT ENERGY CALCULATION Integration Time Under Steady Load: Apparent Energy Apparent Energy Pulse Output Line Apparent Energy Accumulation Apparent Power No Load Detection AMPERE HOUR ACCUMULATION ENERGY TO FREQUENCY CONVERSION Pulse Output Configuration Pulse Output Characteristic ENERGY REGISTER SCALING ENERGY MEASUREMENT INTERRUPTS TEMPERATURE, BATTERY, AND SUPPLY VOLTAGE MEASUREMENTS TEMPERATURE MEASUREMENT Single Temperature Measurement Background Temperature Measurements Temperature ADC in PSM0, PSM1, and PSM2 Temperature ADC Interrupt BATTERY MEASUREMENT Single Battery Measurement Background Battery Measurements Battery ADC in PSM0, PSM1, and PSM2 Modes Battery ADC Interrupt EXTERNAL VOLTAGE MEASUREMENT Single External Voltage Measurement Background External Voltage Measurements External Voltage ADC in PSM0, PSM1, and PSM2 Modes External Voltage ADC Interrupt 8052 MCU CORE ARCHITECTURE MCU REGISTERS BASIC 8052 REGISTERS Program Counter (PC) Instruction Register (IR) Register Banks Accumulator B Register Program Status Word (PSW) Data Pointer (DPTR) Stack Pointer (SP) STANDARD 8052 SFRs Timer SFRs Serial Port SFRs Interrupt SFRs I/O Port SFRs Power Control Register (PCON, Address 0x87) MEMORY OVERVIEW General-Purpose RAM Special Function Registers (SFRs) Extended Internal RAM (XRAM) Code Memory ADDRESSING MODES Immediate Addressing Direct Addressing Indirect Addressing Extended Direct Addressing Extended Indirect Addressing Code Indirect Addressing INSTRUCTION SET READ-MODIFY-WRITE INSTRUCTIONS INSTRUCTIONS THAT AFFECT FLAGS ADD A, Source ADDC A, Source SUBB A, Source MUL AB DIV AB DA A RRC A RLC A CJNE Destination, Source, Relative Jump DUAL DATA POINTERS INTERRUPT SYSTEM STANDARD 8052 INTERRUPT ARCHITECTURE INTERRUPT ARCHITECTURE INTERRUPT REGISTERS INTERRUPT PRIORITY INTERRUPT FLAGS INTERRUPT VECTORS INTERRUPT LATENCY CONTEXT SAVING WATCHDOG TIMER Writing to the Watchdog Timer SFR (WDCON, Address 0xC0) Watchdog Timer Interrupt LCD DRIVER LCD REGISTERS LCD SETUP LCD TIMING AND WAVEFORMS BLINK MODE Software Controlled Blink Mode Automatic Blink Mode DISPLAY ELEMENT CONTROL Writing to LCD Data Registers Reading LCD Data Registers VOLTAGE GENERATION Lifetime Performance Power Consumption Contrast Control Lifetime Performance LCD EXTERNAL CIRCUITRY Charge Pump External Resistor Ladder LCD FUNCTION IN PSM2 MODE Example LCD Setup FLASH MEMORY FLASH MEMORY OVERVIEW Flash/EE Memory Reliability FLASH MEMORY ORGANIZATION USING THE FLASH MEMORY ECON—Flash Control SFR Flash Functions Write Byte Erase Page Erase All Read Byte Erase Page and Write Byte PROTECTING THE FLASH MEMORY Enabling Flash Protection by Code Enabling Flash Protection by Emulator Commands Notes on Flash Protection Flash Memory Timing IN CIRCUIT PROGRAMMING Serial Downloading TIMERS TIMER REGISTERS TIMER 0 AND TIMER 1 Timer 0 High/Low and Timer 1 High/Low Data SFRs Timer/Counter 0 and Timer/Counter 1 Operating Modes Mode 0 (13-Bit Timer/Counter) Mode 1 (16-Bit Timer/Counter) Mode 2 (8-Bit Timer/Counter with Autoreload) Mode 3 (Two 8-Bit Timer/Counters) TIMER 2 Timer/Counter 2 Data Registers Timer/Counter 2 Operating Modes 16-Bit Autoreload Mode 16-Bit Capture Mode PHASE-LOCKED LOOP (PLL) PLL REGISTERS REAL-TIME CLOCK (RTC) RTC SFRS Protecting the RTC from Runaway Code READ AND WRITE OPERATIONS Writing to the RTC Registers Reading the RTC Counter SFRs RTC MODES RTC INTERRUPTS Interval Timer Alarm RTC CALIBRATION Calibrating the RTC Calibration Flow UART SERIAL INTERFACE UART SFRS UART OPERATION MODES Mode 0 (Shift Register with Baud Rate Fixed at fCORE/12) Mode 1 (8-Bit UART, Variable Baud Rate) Mode 2 (9-Bit UART with Baud Fixed at fCORE/64 or fCORE/32) Mode 3 (9-Bit UART with Variable Baud Rate) UART BAUD RATE GENERATION Mode 0 Baud Rate Generation Mode 2 Baud Rate Generation Mode 1 and Mode 3 Baud Rate Generation Timer 1 Generated Baud Rates Timer 2 Generated Baud Rates UART Timer Generated Baud Rates UART ADDITIONAL FEATURES Enhanced Error Checking UART TxD Signal Modulation SERIAL PERIPHERAL INTERFACE (SPI) SPI REGISTERS SPI PINS MISO (Master In, Slave Out Data I/O Pin) MOSI (Master Out, Slave In Pin) SCLK (Serial Clock I/O Pin) /SS (Slave Select Pin) SPI MASTER OPERATING MODES Procedures for Using SPI as a Master Single Byte Write Mode, SPICONT (SPIMOD2[7]) = 0 Continuous Mode, SPICONT (SPIMOD2[7]) = 1 SPI INTERRUPT AND STATUS FLAGS I2C-COMPATIBLE INTERFACE SERIAL CLOCK GENERATION SLAVE ADDRESSES I2C REGISTERS READ AND WRITE OPERATIONS Reading the SPI/I2C Receive Buffer SFR (SPI2CRx, Address 0x9B) I2C RECEIVE AND TRANSMIT FIFOS I/O PORTS PARALLEL I/O Weak Internal Pull-Ups Enabled Open Drain (Weak Internal Pull-Ups Disabled) 38 kHz Modulation I/O REGISTERS PORT 0 PORT 1 PORT 2 DETERMINING THE VERSION OF THE DEVICE OUTLINE DIMENSIONS ORDERING GUIDE