Datasheet AD8370 (Analog Devices) - 3
| 制造商 | Analog Devices |
| 描述 | 750 MHz Digitally Controlled Variable Gain Amplifier |
| 页数 / 页 | 28 / 3 — Data Sheet. AD8370. SPECIFICATIONS. Table 1. Parameter. Conditions. Min. … |
| 修订版 | B |
| 文件格式/大小 | PDF / 786 Kb |
| 文件语言 | 英语 |
Data Sheet. AD8370. SPECIFICATIONS. Table 1. Parameter. Conditions. Min. Typ. Max. Unit
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Data Sheet AD8370 SPECIFICATIONS
VS = 5 V, T = 25°C, ZS = 200 Ω, ZL = 100 Ω at gain code HG127, 70 MHz, 1 V p-p differential output, unless otherwise noted.
Table 1. Parameter Conditions Min Typ Max Unit
DYNAMIC PERFORMANCE −3 dB Bandwidth VOUT < 1 V p-p 750 MHz Slew Rate Gain Code HG127, RL = 1 kΩ, AD8370 in compression 5.75 V/ns Gain Code LG127, RL = 1 kΩ, VOUT = 2 V p-p 3.5 V/ns INPUT STAGE Pins INHI and IHLO Maximum Input Gain Code LG2, 1 dB compression 3.2 V p-p Input Resistance Differential 200 Ω Common-Mode Input Range 3.2 V p-p CMRR Differential, f = 10 MHz, Gain Code LG127 77 dB Input Noise Spectral Density 1.9 nV/√Hz GAIN Maximum Voltage Gain High Gain Mode Gain Code = HG127 34 dB 52 V/V Low Gain Mode Gain Code = LG127 17 dB 7.4 V/V Minimum Voltage Gain High Gain Mode Gain Code = HG1 −8 dB 0.4 V/V Low Gain Mode Gain Code = LG1 −25 dB 0.06 V/V Gain Step Size High Gain Mode 0.408 (V/V)/Code Low Gain Mode 0.056 (V/V)/Code Gain Temperature Sensitivity Gain Code = HG127 –2 mdB/°C Step Response For 6 dB gain step, settled to 10% of final value 20 ns OUTPUT INTERFACE Pins OPHI and OPLO Output Voltage Swing RL ≥ 1 kΩ (1 dB compression) 8.4 V p-p Output Resistance Differential 95 Ω Output Differential Offset VINHI = VINLO, over all gain codes ±60 mV NOISE/HARMONIC PERFORMANCE 10 MHz Gain Flatness Within ±10 MHz of 10 MHz ±0.01 dB Noise Figure 7.2 dB Second Harmonic1 VOUT = 2 V p-p −77 dBc Third Harmonic1 VOUT = 2 V p-p −77 dBc Output IP3 35 dBm Output 1 dB Compression Point 17 dBm 70 MHz Gain Flatness Within ±10 MHz of 70 MHz ±0.02 dB Noise Figure 7.2 dB Second Harmonic1 VOUT = 2 V p-p −65 dBc Third Harmonic1 VOUT = 2 V p-p −62 dBc Output IP3 35 dBm Output 1 dB Compression Point 17 dBm Rev. B | Page 3 of 28 Document Outline Features Applications General Description Functional Block Diagram Table of Contents Revision History Specifications Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Block Architecture Preamplifier Transconductance Stage Output Amplifier Digital Interface and Timing Applications Basic Connections Gain Codes Power-Up Feature Choosing Between Gain Ranges Layout and Operating Considerations Package Considerations Single-Ended-to-Differential Conversion DC-Coupled Operation ADC Interfacing 3 V Operation Evaluation Board and Software Appendix Characterization Equipment Composite Waveform Assumption Definitions of Selected Parameters Outline Dimensions Ordering Guide
Data Sheet AD8370 SPECIFICATIONS
VS = 5 V, T = 25°C, ZS = 200 Ω, ZL = 100 Ω at gain code HG127, 70 MHz, 1 V p-p differential output, unless otherwise noted.
Table 1. Parameter Conditions Min Typ Max Unit
DYNAMIC PERFORMANCE −3 dB Bandwidth VOUT < 1 V p-p 750 MHz Slew Rate Gain Code HG127, RL = 1 kΩ, AD8370 in compression 5.75 V/ns Gain Code LG127, RL = 1 kΩ, VOUT = 2 V p-p 3.5 V/ns INPUT STAGE Pins INHI and IHLO Maximum Input Gain Code LG2, 1 dB compression 3.2 V p-p Input Resistance Differential 200 Ω Common-Mode Input Range 3.2 V p-p CMRR Differential, f = 10 MHz, Gain Code LG127 77 dB Input Noise Spectral Density 1.9 nV/√Hz GAIN Maximum Voltage Gain High Gain Mode Gain Code = HG127 34 dB 52 V/V Low Gain Mode Gain Code = LG127 17 dB 7.4 V/V Minimum Voltage Gain High Gain Mode Gain Code = HG1 −8 dB 0.4 V/V Low Gain Mode Gain Code = LG1 −25 dB 0.06 V/V Gain Step Size High Gain Mode 0.408 (V/V)/Code Low Gain Mode 0.056 (V/V)/Code Gain Temperature Sensitivity Gain Code = HG127 –2 mdB/°C Step Response For 6 dB gain step, settled to 10% of final value 20 ns OUTPUT INTERFACE Pins OPHI and OPLO Output Voltage Swing RL ≥ 1 kΩ (1 dB compression) 8.4 V p-p Output Resistance Differential 95 Ω Output Differential Offset VINHI = VINLO, over all gain codes ±60 mV NOISE/HARMONIC PERFORMANCE 10 MHz Gain Flatness Within ±10 MHz of 10 MHz ±0.01 dB Noise Figure 7.2 dB Second Harmonic1 VOUT = 2 V p-p −77 dBc Third Harmonic1 VOUT = 2 V p-p −77 dBc Output IP3 35 dBm Output 1 dB Compression Point 17 dBm 70 MHz Gain Flatness Within ±10 MHz of 70 MHz ±0.02 dB Noise Figure 7.2 dB Second Harmonic1 VOUT = 2 V p-p −65 dBc Third Harmonic1 VOUT = 2 V p-p −62 dBc Output IP3 35 dBm Output 1 dB Compression Point 17 dBm Rev. B | Page 3 of 28 Document Outline Features Applications General Description Functional Block Diagram Table of Contents Revision History Specifications Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Block Architecture Preamplifier Transconductance Stage Output Amplifier Digital Interface and Timing Applications Basic Connections Gain Codes Power-Up Feature Choosing Between Gain Ranges Layout and Operating Considerations Package Considerations Single-Ended-to-Differential Conversion DC-Coupled Operation ADC Interfacing 3 V Operation Evaluation Board and Software Appendix Characterization Equipment Composite Waveform Assumption Definitions of Selected Parameters Outline Dimensions Ordering Guide