Datasheet AD8370 (Analog Devices) - 4
| 制造商 | Analog Devices |
| 描述 | 750 MHz Digitally Controlled Variable Gain Amplifier |
| 页数 / 页 | 28 / 4 — AD8370. Data Sheet. Parameter. Conditions. Min. Typ. Max. Unit |
| 修订版 | B |
| 文件格式/大小 | PDF / 786 Kb |
| 文件语言 | 英语 |
AD8370. Data Sheet. Parameter. Conditions. Min. Typ. Max. Unit
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AD8370 Data Sheet Parameter Conditions Min Typ Max Unit
140 MHz Gain Flatness Within ±10 MHz of 140 MHz ±0.03 dB Noise Figure 7.2 dB Second Harmonic1 VOUT = 2 V p-p −54 dBc Third Harmonic1 VOUT = 2 V p-p −50 dBc Output IP3 33 dBm Output 1 dB Compression Point 17 dBm 190 MHz Gain Flatness Within ±10 MHz of 240 MHz ±0.03 dB Noise Figure 7.2 dB Second Harmonic1 VOUT = 2 V p-p −43 dBc Third Harmonic1 VOUT = 2 V p-p −43 dBc Output IP3 33 dBm Output 1 dB Compression Point 17 dBm 240 MHz Gain Flatness Within ±10 MHz of 240 MHz ±0.04 dB Noise Figure 7.4 dB Second Harmonic1 VOUT = 2 V p-p –28 dBc Third Harmonic1 VOUT = 2 V p-p –33 dBc Output IP3 32 dBm Output 1 dB Compression Point 17 dBm 380 MHz Gain Flatness Within ±10 MHz of 240 MHz ±0.04 dB Noise Figure 8.1 dB Output IP3 27 dBm Output 1 dB Compression Point 14 dBm POWER-INTERFACE Supply Voltage 3.02 5.5 V Quiescent Current3 PWUP High, GC = LG127, RL = ∞, 4 seconds after 72.5 79 85.5 mA power-on, thermal connection made to exposed paddle under device vs. Temperature4 −40°C ≤ TA ≤ +85°C 105 mA Total Supply Current PWUP High, VOUT = 1 V p-p, ZL = 100 Ω reactive, 82 mA GC = LG127 (includes load current) Power-Down Current PWUP low 3.7 mA vs. Temperature4 −40°C ≤TA ≤ +85°C 5 mA POWER-UP INTERFACE Pin PWUP Power-Up Threshold4 Voltage to enable the device 1.8 V Power-Down Threshold4 Voltage to disable the device 0.8 V PWUP Input Bias Current PWUP = 0 V 400 nA GAIN CONTROL INTERFACE Pins CLCK, DATA, and LTCH V 4 IH Voltage for a logic high 1.8 V V 4 IL Voltage for a logic low 0.8 V Input Bias Current 900 nA 1 Refer to Figure 22 for performance into a lighter load. 2 See the 3 V Operation section for more information. 3 Minimum and maximum specified limits for this parameter are guaranteed by production test. 4 Minimum or maximum specified limit for this parameter is a 6-sigma value and not guaranteed by production test. Rev. B | Page 4 of 28 Document Outline Features Applications General Description Functional Block Diagram Table of Contents Revision History Specifications Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Block Architecture Preamplifier Transconductance Stage Output Amplifier Digital Interface and Timing Applications Basic Connections Gain Codes Power-Up Feature Choosing Between Gain Ranges Layout and Operating Considerations Package Considerations Single-Ended-to-Differential Conversion DC-Coupled Operation ADC Interfacing 3 V Operation Evaluation Board and Software Appendix Characterization Equipment Composite Waveform Assumption Definitions of Selected Parameters Outline Dimensions Ordering Guide
AD8370 Data Sheet Parameter Conditions Min Typ Max Unit
140 MHz Gain Flatness Within ±10 MHz of 140 MHz ±0.03 dB Noise Figure 7.2 dB Second Harmonic1 VOUT = 2 V p-p −54 dBc Third Harmonic1 VOUT = 2 V p-p −50 dBc Output IP3 33 dBm Output 1 dB Compression Point 17 dBm 190 MHz Gain Flatness Within ±10 MHz of 240 MHz ±0.03 dB Noise Figure 7.2 dB Second Harmonic1 VOUT = 2 V p-p −43 dBc Third Harmonic1 VOUT = 2 V p-p −43 dBc Output IP3 33 dBm Output 1 dB Compression Point 17 dBm 240 MHz Gain Flatness Within ±10 MHz of 240 MHz ±0.04 dB Noise Figure 7.4 dB Second Harmonic1 VOUT = 2 V p-p –28 dBc Third Harmonic1 VOUT = 2 V p-p –33 dBc Output IP3 32 dBm Output 1 dB Compression Point 17 dBm 380 MHz Gain Flatness Within ±10 MHz of 240 MHz ±0.04 dB Noise Figure 8.1 dB Output IP3 27 dBm Output 1 dB Compression Point 14 dBm POWER-INTERFACE Supply Voltage 3.02 5.5 V Quiescent Current3 PWUP High, GC = LG127, RL = ∞, 4 seconds after 72.5 79 85.5 mA power-on, thermal connection made to exposed paddle under device vs. Temperature4 −40°C ≤ TA ≤ +85°C 105 mA Total Supply Current PWUP High, VOUT = 1 V p-p, ZL = 100 Ω reactive, 82 mA GC = LG127 (includes load current) Power-Down Current PWUP low 3.7 mA vs. Temperature4 −40°C ≤TA ≤ +85°C 5 mA POWER-UP INTERFACE Pin PWUP Power-Up Threshold4 Voltage to enable the device 1.8 V Power-Down Threshold4 Voltage to disable the device 0.8 V PWUP Input Bias Current PWUP = 0 V 400 nA GAIN CONTROL INTERFACE Pins CLCK, DATA, and LTCH V 4 IH Voltage for a logic high 1.8 V V 4 IL Voltage for a logic low 0.8 V Input Bias Current 900 nA 1 Refer to Figure 22 for performance into a lighter load. 2 See the 3 V Operation section for more information. 3 Minimum and maximum specified limits for this parameter are guaranteed by production test. 4 Minimum or maximum specified limit for this parameter is a 6-sigma value and not guaranteed by production test. Rev. B | Page 4 of 28 Document Outline Features Applications General Description Functional Block Diagram Table of Contents Revision History Specifications Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Block Architecture Preamplifier Transconductance Stage Output Amplifier Digital Interface and Timing Applications Basic Connections Gain Codes Power-Up Feature Choosing Between Gain Ranges Layout and Operating Considerations Package Considerations Single-Ended-to-Differential Conversion DC-Coupled Operation ADC Interfacing 3 V Operation Evaluation Board and Software Appendix Characterization Equipment Composite Waveform Assumption Definitions of Selected Parameters Outline Dimensions Ordering Guide