Datasheet ADP5052 (Analog Devices)

5-Channel Integrated Power Solution with Quad Buck Regulators and 200 mA LDO Regulator Data Sheet ADP5052 FEATURES TYPICAL APPLICATION CIRCUIT Wide input voltage range: 4.5 V to 15 V ADP5052 SYNC/MODE VREG ±1.5% output accuracy over full temperature range INT VREG VDD OSCILLATOR C1 100mA RT 250 kHz to 1.4 MHz adjustable switching frequency C0 FB1 Adjustable/fixed output options via factory fuse PVIN1 4.5V TO 15V BST1 Power regulation SW1 CHANNEL 1 C3 L1 C2 VOUT1 BUCK REGULATOR COMP1 Channel 1 and Channel 2: programmable 1.2 A/2.5 A/4 A (1.2A/2.5A/4A) VREG C4 EN1 Q1 DL1 sync buck regulators with low-side FET driver SS12 RILIM1 Channel 3 and Channel 4: 1.2 A sync buck regulators PGND R DL2 ILIM2 Channel 5: 200 mA low dropout (LDO) regulator Q2 PVIN2 Always alive 5.1 V LDO supply for tiny load demand C5 CHANNEL 2 VREG SW2 VOUT2 BUCK REGULATOR COMP2 L2 Single 8 A output (Channel 1 and Channel 2 operated (1.2A/2.5A/4A) C6 C7 BST2 EN2 in parallel) FB2 PWRGD Precision enable with 0.8 V accurate threshold PVIN3 BST3 Active output discharge switch C8 C9 L3 VOUT3 COMP3 CHANNEL 3 SW3 FPWM or automatic PWM/PSM mode selection BUCK REGULATOR C10 (1.2A) FB3 EN3 Frequency synchronization input or output PGND3 SS34 Optional latch-off protection on OVP/OCP failure BST4 Power-good flag on selected channels PVIN4 C12 L4 SW4 VOUT4 CHANNEL 4 C11 UVLO, OCP, and TSD protection BUCK REGULATOR COMP4 FB4 C13 (1.2A) 48-lead, 7 mm × 7 mm LFCSP package EN4 PGND4 −40°C to +125°C junction temperature 1.7V TO 5.5V PVIN5 VOUT5 VOUT5 CHANNEL 5 EN5 200mA LDO C14 FB5 C15 APPLICATIONS REGULATOR Small cell base stations
001
EXPOSED PAD
10900-
FPGA and processor applications
Figure 1.
Security and surveillance Medical applications GENERAL DESCRIPTION
The ADP5052 combines four high performance buck regulators The switching frequency of the ADP5052 can be programmed and one 200 mA low dropout (LDO) regulator in a 48-lead LFCSP or synchronized to an external clock. The ADP5052 contains a package that meets demanding performance and board space precision enable pin on each channel for easy power-up sequencing requirements. The device enables direct connection to high input or adjustable UVLO threshold. voltages up to 15 V with no preregulators. The ADP5052 integrates a general-purpose LDO regulator with Channel 1 and Channel 2 integrate high-side power MOSFETs and low quiescent current and low dropout voltage that provides up low-side MOSFET drivers. External NFETs can be used in low-side to 200 mA of output current. power devices to achieve an efficiency optimized solution and deliver a programmable output current of 1.2 A, 2.5 A, or 4 A.
Table 1. Family Models
Combining Channel 1 and Channel 2 in a paral el configuration
Model Channels I2C Package
can provide a single output with up to 8 A of current. ADP5050 Four bucks, one LDO Yes 48-Lead LFCSP ADP5051 Four bucks, supervisory Yes 48-Lead LFCSP Channel 3 and Channel 4 integrate both high-side and low-side ADP5052 Four bucks, one LDO No 48-Lead LFCSP MOSFETs to deliver output current of 1.2 A. ADP5053 Four bucks, supervisory No 48-Lead LFCSP ADP5054 Four high current bucks No 48-Lead LFCSP
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Document Outline FEATURES APPLICATIONS TYPICAL APPLICATION CIRCUIT GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY DETAILED FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS BUCK REGULATOR SPECIFICATIONS LDO REGULATOR SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION BUCK REGULATOR OPERATIONAL MODES PWM Mode PSM Mode Forced PWM and Automatic PWM/PSM Modes ADJUSTABLE AND FIXED OUTPUT VOLTAGES INTERNAL REGULATORS (VREG AND VDD) SEPARATE SUPPLY APPLICATIONS LOW-SIDE DEVICE SELECTION BOOTSTRAP CIRCUITRY ACTIVE OUTPUT DISCHARGE SWITCH PRECISION ENABLING OSCILLATOR Phase Shift SYNCHRONIZATION INPUT/OUTPUT SOFT START PARALLEL OPERATION STARTUP WITH PRECHARGED OUTPUT CURRENT-LIMIT PROTECTION FREQUENCY FOLDBACK Pulse Skip Mode Under Maximum Duty Cycle HICCUP PROTECTION LATCH-OFF PROTECTION Short-Circuit Latch-Off Mode Overvoltage Latch-Off Mode UNDERVOLTAGE LOCKOUT (UVLO) POWER-GOOD FUNCTION THERMAL SHUTDOWN LDO REGULATOR APPLICATIONS INFORMATION ADIsimPower DESIGN TOOL PROGRAMMING THE ADJUSTABLE OUTPUT VOLTAGE VOLTAGE CONVERSION LIMITATIONS CURRENT-LIMIT SETTING SOFT START SETTING INDUCTOR SELECTION OUTPUT CAPACITOR SELECTION INPUT CAPACITOR SELECTION LOW-SIDE POWER DEVICE SELECTION PROGRAMMING THE UVLO INPUT COMPENSATION COMPONENTS DESIGN POWER DISSIPATION Buck Regulator Power Dissipation Power Switch Conduction Loss (PCOND) Switching Loss (PSW) Transition Loss (PTRAN) Thermal Shutdown LDO Regulator Power Dissipation JUNCTION TEMPERATURE DESIGN EXAMPLE SETTING THE SWITCHING FREQUENCY SETTING THE OUTPUT VOLTAGE SETTING THE CURRENT LIMIT SELECTING THE INDUCTOR SELECTING THE OUTPUT CAPACITOR SELECTING THE LOW-SIDE MOSFET DESIGNING THE COMPENSATION NETWORK SELECTING THE SOFT START TIME SELECTING THE INPUT CAPACITOR RECOMMENDED EXTERNAL COMPONENTS CIRCUIT BOARD LAYOUT RECOMMENDATIONS TYPICAL APPLICATION CIRCUITS FACTORY DEFAULT OPTIONS OUTLINE DIMENSIONS ORDERING GUIDE