Datasheet ADP5052 (Analog Devices) - 3

Data Sheet ADP5052 DETAILED FUNCTIONAL BLOCK DIAGRAM CHANNEL 1 BUCK REGULATOR UVLO1 PVIN1 0.8V – + EN1 + ACS1 – 1MΩ VREG HICCUP + BST1 AND CLK1 OCP – LATCH-OFF Q1 DRIVER SLOPE COMP + SW1 CMP1 Q E DG1 CONTROL LOGIC H COMP1 – C AND MOSFET VREG IT DRIVER WITH CHARG W 0.8V + CLK1 S S EA1 ANTICROSS DI – DRIVER FB1 PROTECTION DL1 FREQUENCY PGND FOLDBACK ZERO OVP CROSS + LATCH-OFF VID1 – + 0.99V CURRENT-LIMIT 0.72V – PWRGD1 SELECTION CURRENT BALANCE PVIN2 EN2 CHANNEL 2 BUCK REGULATOR BST2 COMP2 DUPLICATE CHANNEL 1 DL2 FB2 SW2 RT OSCILLATOR VREG SYNC/MODE PVIN1 VREG SS12 INTERNAL SOFT START HOUSEKEEPING REGULATOR DECODER LOGIC SS34 VDD PWRGD QPWRGD CHANNEL 3 BUCK REGULATOR UVLO3 PVIN3 0.8V – + EN3 + ACS3 – 1MΩ VREG HICCUP + BST3 AND CLK3 OCP – LATCH-OFF Q3 DRIVER SLOPE COMP + CMP3 SW3 CONTROL LOGIC COMP3 – AND MOSFET VREG DRIVER WITH Q4 0.8V + CLK3 EA3 ANTICROSS DRIVER FB3 – PROTECTION FREQUENCY PGND3 FOLDBACK OVP ZERO + LATCH-OFF CROSS E VID3 H – + 0.99V C IT CHARG W – Q 0.72V S S PWRGD3 DG3 DI EN4 CHANNEL 4 BUCK REGULATOR PVIN4 BST4 DUPLICATE CHANNEL 3 COMP4 SW4 FB4 PGND4 CHANNEL 5 LDO REGULATOR PVIN5 VOUT5 0.8V – LDO Q7 – 0.5V CONTROL EN5 + EA5+ FB5 1MΩ
202 10900- Figure 2. Rev. D | Page 3 of 36 Document Outline FEATURES APPLICATIONS TYPICAL APPLICATION CIRCUIT GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY DETAILED FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS BUCK REGULATOR SPECIFICATIONS LDO REGULATOR SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION BUCK REGULATOR OPERATIONAL MODES PWM Mode PSM Mode Forced PWM and Automatic PWM/PSM Modes ADJUSTABLE AND FIXED OUTPUT VOLTAGES INTERNAL REGULATORS (VREG AND VDD) SEPARATE SUPPLY APPLICATIONS LOW-SIDE DEVICE SELECTION BOOTSTRAP CIRCUITRY ACTIVE OUTPUT DISCHARGE SWITCH PRECISION ENABLING OSCILLATOR Phase Shift SYNCHRONIZATION INPUT/OUTPUT SOFT START PARALLEL OPERATION STARTUP WITH PRECHARGED OUTPUT CURRENT-LIMIT PROTECTION FREQUENCY FOLDBACK Pulse Skip Mode Under Maximum Duty Cycle HICCUP PROTECTION LATCH-OFF PROTECTION Short-Circuit Latch-Off Mode Overvoltage Latch-Off Mode UNDERVOLTAGE LOCKOUT (UVLO) POWER-GOOD FUNCTION THERMAL SHUTDOWN LDO REGULATOR APPLICATIONS INFORMATION ADIsimPower DESIGN TOOL PROGRAMMING THE ADJUSTABLE OUTPUT VOLTAGE VOLTAGE CONVERSION LIMITATIONS CURRENT-LIMIT SETTING SOFT START SETTING INDUCTOR SELECTION OUTPUT CAPACITOR SELECTION INPUT CAPACITOR SELECTION LOW-SIDE POWER DEVICE SELECTION PROGRAMMING THE UVLO INPUT COMPENSATION COMPONENTS DESIGN POWER DISSIPATION Buck Regulator Power Dissipation Power Switch Conduction Loss (PCOND) Switching Loss (PSW) Transition Loss (PTRAN) Thermal Shutdown LDO Regulator Power Dissipation JUNCTION TEMPERATURE DESIGN EXAMPLE SETTING THE SWITCHING FREQUENCY SETTING THE OUTPUT VOLTAGE SETTING THE CURRENT LIMIT SELECTING THE INDUCTOR SELECTING THE OUTPUT CAPACITOR SELECTING THE LOW-SIDE MOSFET DESIGNING THE COMPENSATION NETWORK SELECTING THE SOFT START TIME SELECTING THE INPUT CAPACITOR RECOMMENDED EXTERNAL COMPONENTS CIRCUIT BOARD LAYOUT RECOMMENDATIONS TYPICAL APPLICATION CIRCUITS FACTORY DEFAULT OPTIONS OUTLINE DIMENSIONS ORDERING GUIDE